Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMessaging Unit6.8 Register DefinitionsThe following registers are located in the primary PCI address space and in the PeripheralMemory-Mapped Register (PMMR) address space. They are accessible through primary PCI bustransactions and through Intel ® 80200 processor internal bus accesses. In the primary PCI addressspace, they are mapped into the first 80 bytes of the primary inbound address window of thePrimary ATU.• Inbound Message 0 Register• Inbound Message 1 Register• Outbound Message 0 Register• Outbound Message 1 Register• Inbound Doorbell Register• Inbound Interrupt Status Register• Inbound Interrupt Mask Register• Outbound Doorbell Register• Outbound Interrupt Status Register• Outbound Interrupt Mask RegisterThe following registers are located in the Peripheral Memory-Mapped Register (PMMR) addressspace as described in Appendix A, “Peripheral Memory-Mapped Registers”.• MU Configuration Register• Queue Base Address Register• Inbound Free Head Pointer Register• Inbound Free Tail Pointer Register• Inbound Post Head Pointer Register• Inbound Post Tail Pointer Register• Outbound Free Head Pointer Register• Outbound Free Tail Pointer Register• Outbound Post Head Pointer Register• Outbound Post Tail Pointer Register• Index Address RegisterReading or writing a register that is reserved is undefined.6-16 Developer’s Manual
Intel ® 80312 I/O Companion ChipMessaging UnitTable 6-6.Message Unit Register TableLocal BusAddressSection, Register Name - Acronym (Page)1310H Section 6.8.1, “Inbound Message Register - IMRx” on page 6-181314H Section 6.8.1, “Inbound Message Register - IMRx” on page 6-181318H Section 6.8.2, “Outbound Message Register - OMRx” on page 6-19131CH Section 6.8.2, “Outbound Message Register - OMRx” on page 6-191320H Section 6.8.3, “Inbound Doorbell Register - IDR” on page 6-201324H Section 6.8.4, “Inbound Interrupt Status Register - IISR” on page 6-211328H Section 6.8.5, “Inbound Interrupt Mask Register - IIMR” on page 6-22132CH Section 6.8.6, “Outbound Doorbell Register - ODR” on page 6-231330H Section 6.8.7, “Outbound Interrupt Status Register - OISR” on page 6-241334H Section 6.8.8, “Outbound Interrupt Mask Register - OIMR” on page 6-251350H Section 6.8.9, “MU Configuration Register - MUCR” on page 6-261354H Section 6.8.10, “Queue Base Address Register - QBAR” on page 6-271360H Section 6.8.11, “Inbound Free Head Pointer Register - IFHPR” on page 6-281364H Section 6.8.12, “Inbound Free Tail Pointer Register - IFTPR” on page 6-291368H Section 6.8.13, “Inbound Post Head Pointer Register - IPHPR” on page 6-30136CH Section 6.8.14, “Inbound Post Tail Pointer Register - IPTPR” on page 6-311370H Section 6.8.15, “Outbound Free Head Pointer Register - OFHPR” on page 6-321374H Section 6.8.16, “Outbound Free Tail Pointer Register - OFTPR” on page 6-331378H Section 6.8.17, “Outbound Post Head Pointer Register - OPHPR” on page 6-34137CH Section 6.8.18, “Outbound Post Tail Pointer Register - OPTPR” on page 6-351380H Section 6.8.19, “Index Address Register - IAR” on page 6-36Developer’s Manual 6-17
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