Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.5.2 Intel ® 80200 Processor Request Bus WriteThe Intel ® 80200 processor request bus issues a write command.1. On the rising-edge of clock 1, the Intel ® 80200 processor asserts active low ADS# to indicatea valid request bus command. The Intel ® 80200 processor (for write) asserts active highW/R#. TheLOCK# signal is deasserted indicating that the write is not completing a lockedatomic read modify write.2. Concurrent with the rising clock edge above, the Intel ® 80200 processor asserts the mostsignificant 16 bits of address on ADD[15:0]. This address is translated by the CIU to internalbus address bits [31:16] (I_AD[31:16]).3. On the rising edge of clock 2, the Intel ® 80200 processor asserts the request transfer length onADS#, W/R# and LOCK#. The least significant 16 bits of address are driven on ADD[15:0].This address is translated by the CIU to internal bus address bits 15:0.4. The CIU asserts the C_HOLDMCU sideband signal to obtain ownership of the SDRAM bus.5. The MCU acknowledges that it is ready to allow the CIU write transaction by asserting theM_HOLDACK sideband signal.6. CIU asserts dvalid.7. CIU asserts (active low, MC path) M_DATE# to take ownership of the data bus outputdrivers. The MCU disables it’s data bus drivers, sending data bus signals and SCB into hi-zstate.8. The Intel ® 80200 processor provides write data on the rising edge of the clock 2 clock periodsafter dvalid is sampled. The CIU controls the direction of the transfer with C_DQE#.9. The CIU deasserts C_DQE# and M_DATE#. the data bus and SCB float for one cycle.10. The CIU issues a request for ownership of the internal PCI bus to the arbiter.11. The Arbiter grants ownership of the internal bus to the CIU.12. The CIU asserts frame on the internal bus and supplies the appropriate PCI command -“memory write” for transaction of 8 bytes. Memory write and invalidate is never used by theCIU on the internal bus.13. The CIU asserts the internal bus I_IRDY# signal indicating that as initiator it is ready totransmit data.14. The MCU claims the internal bus transaction by asserting I_DEVSEL#.15. The CIU asserts data and byte enables on the internal bus.16. The MCU asserts I_TRDY# and captures the write data.17. The CIU de-asserts C_HOLDMCU.18. The MCU de-asserts M_HOLDACK.19. The CIU removes the internal bus request.20. Grant is deasserted (CIU is the default internal bus master, grant parks on the CIU unless otheragents request).21. CIU returns to idle. If an outstanding command exist in the queue, that command is initiated.22. The MCU provides row and column address for the SDRAM and completes the access.8-8 Developer’s Manual