Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and Initialization15.1.1 Clocking Theory of OperationEach region within the Intel ® 80312 I/O companion chip contains different clocking requirements.These requirements are summarized in the following sections.15.1.2 Clocking Region 1Region 1 contains the main input clock for providing the Intel ® 80312 I/O companion chip with allof its clock sources. This input clock is provided by the system designer. This input clock, calledthe primary PCI bus clock, is connected to the input pin P_CLK.TheIntel ® 80312 I/O companionchip supports an input frequency of 33 MHz or 66 MHz for normal PCI bus operation on theprimary PCI interface. For the Intel ® 80312 I/O companion chip, region 1 obtains its input clock asa buffered version of P_CLK.15.1.3 Clocking Region 2Region 2 obtains its input clock from the clocking unit specified in clocking region 1. This regionis the Intel ® 80312 I/O companion chip internal bus. It supports clock frequency operations to amaximum of 100 MHz. The clocking unit provides five SDRAM output clocks, based on adedicated PLL. The clocking unit contains five output clocks, called DCLK[3:0], DCLKOUT andone SDRAM input clock called DCLKIN. TheDCLK[3:0] and DCLKOUT outputs are used bySDRAM memory subsystem. The DCLKOUT signal is routed back into DCLKIN, to skew matchthe DCLKIN input to the clock outputs in the memory subsystem to properly accommodate forflight time delays. Refer to Figure 15-2 for a diagram that describes the SDRAM clockingrequirements.Figure 15-2.SDRAM Clocking DiagramI_CLKDQ(71:0)SDQ(71:0)2Mx8SDRAMSDQ(71:0)DQ(71:0)P_CLKDCLK(3:0)DCLK(3:0)DCLKoutDCLKinSDRAMDIMM0SDRAMDIMM1A8320-0115-2 Developer’s Manual