Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.4 Error Correction and DetectionThe MCU is capable of correcting any single bit errors and detecting any double bit errors in theIntel ® 80312 I/O companion chip SDRAM memory subsystem. In addition, the ECC logic detectsany three or four bit errors which occur in the same nibble. ECC enhances the reliability of amemory subsystem by correcting single bit errors caused by electrical noise or occasional alphaparticle hits on the SDRAM devices.Similar to parity, which simply detects single bit errors, error correction requires an additional 8-bitcode word for the 64-bit datum. This means that a memory must have the additional 8-bit errorcorrection code (SCB[7:0]) per 64-bit datum (DQ[63:0]) resulting in a 72-bit wide memorysubsystem. During SDRAM read cycles, the MCU detects single bit errors and corrects the dataprior to returning the data on the internal bus. SDRAM write cycles generate the ECC and sends itwith the data to the memories.Scrubbing is the process of correcting an error in the memory array. The chance of anunrecoverable multi-bit error increases when the software does not correct a single-bit error in thearray. For the Intel ® 80312 I/O companion chip, scrubbing is handled by software. When an erroroccurs, the MCU logs the error type in ELOG0 or ELOG1 and the address in ECAR0 or ECAR1.3.2.4.1 ECC GenerationFor write operations, the MCU generates the error correction code which is written along with thedata. The algorithm for a write transaction is:if data to write is 64 bits wideGenerate the ECCWrite the new data and ECCelse {Partial Write}Read entire 64-bit data word from memoryMerge the new data portion with the data from memoryGenerate the new ECCWrite new data and ECCDeveloper’s Manual 3-27