Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitTable 5-27. ATU PCI Configuration Register Space (Sheet 2 of 2)LocalBusAddressOffsetATU PCI Configuration Register Section, Name, Page90H Section 5.7.38, “Primary ATU Interrupt Status Register - PATUISR” on page 5-10094H Section 5.7.39, “Secondary ATU Interrupt Status Register - SATUISR” on page 5-10298H Section 5.7.40, “Secondary ATU Command Register - SATUCMD” on page 5-1049AH Section 5.7.41, “Secondary ATU Status Register - SATUSR” on page 5-1059CH Section 5.7.42, “Secondary Outbound DAC Window Value Register - SODWVR” on page 5-106A0H Section 5.7.43, “Secondary Outbound Upper 64-bit DAC Register - SOUDR” on page 5-107A4H Section 5.7.44, “Primary Outbound Configuration Cycle Address Register - POCCAR” on page 5-108A8HSection 5.7.45, “Secondary Outbound Configuration Cycle Address Register - SOCCAR” onpage 5-109ACH Section 5.7.46, “Primary Outbound Configuration Cycle Data Register - POCCDR” on page 5-110B0H Section 5.7.47, “Secondary Outbound Configuration Cycle Data Register - SOCCDR” on page 5-111B4H Section 5.7.48, “Primary ATU Queue Control Register - PAQCR” on page 5-112B8H Section 5.7.49, “Secondary ATU Queue Control Register - SAQCR” on page 5-113BCH Section 5.7.50, “Primary ATU Interrupt Mask Register - PATUIMR” on page 5-114C0H Section 5.7.51, “Secondary ATU Interrupt Mask Register - SATUIMR” on page 5-1155-60 Developer’s Manual