Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.22 Bridge Control Register - BCRBridge Control Register bits provide extensions to the Command Register that are specific toPCI-to-PCI bridges. The Bridge Control Register provides many of the same controls for theSecondary interface that are provided by the Command register for the Primary interface. Somebits affect the operation of both interfaces of the bridge.Table 4-45. Bridge Control Register - BCR (Sheet 1 of 2)IOPAttributes15 12 8 4 0rv rv rv rv rw rc rw rw ro rw rw rv rw rw rw rwPCIAttributesrvrvrvrvrwrcrw rwrorw rwrvrw rwrw rwPCI Configuration Offset3E - 3FHIntel ® 80200 Processor Local Bus Address0000 103EHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:12 0000 2 Reserved.11 0 2Discard Timer SERR# Enable - This bit enables the assertion of P_SERR# for all discard timers. A valueof 0 indicates that P_SERR# is not asserted when any discard timer expires. A value of 1 indicates thatP_SERR# is asserted (when enabled in the PCR) when a discard timer expires.10 0 2Discard Timer Status - This bit indicates the status of the discard timers. A value of zero indicates that nodiscard timers have expired. A value of 1 indicates that at least one of the eight discard timers hasexpired.09 0 2Secondary Discard Timer Value - This bit controls the time-out value for the four discard timers attachedto the queues holding data for transactions initiated on the Secondary bus. A value of zero indicates thetime-out value is 2 15 clocks. A value of 1 indicates the time-out value is 2 10 clocks.08 0 2Primary Discard Timer Value - This bit controls the time-out value for the four discard timers attached tothe queues holding data for transactions initiated on the Primary bus. A value of 0 indicates the time-outvalue is 2 15 clocks. A value of 1 indicates the time-out value is 2 10 clocks.07 0 2 Fast Back to Back Enable - This Secondary interface does not perform fast back to back transactions.06 0 2transactions. It will then return to an idle state. DMA Channel 2 will not begin any new transfers untilthe Secondary Bus Reset bit is cleared.Secondary Bus Reset - This bit controls the Secondary bus S_RST# signal. When set:• The PCI-to-PCI Bridge Unit will reset all upstream and downstream Transaction Queues and DataQueues as well as the Secondary PCI bus interface. The Bridge PCI configuration registers are notreset. The Primary PCI bus interface will retry all transactions, except Type 0 configurationtransactions, until this bit is cleared.• DMA Channel 2 will immediately halt any PCI transactions and gracefully complete any local bus• Secondary ATU will immediately halt any PCI transactions and gracefully complete any local bustransactions. The Intel ® 80200 processor will be released from back-off, when necessary. TheSecondary ATU will not accept any new Intel ® 80200 processor requests until the Secondary BusReset bit is cleared. The Secondary ATU configuration registers are reset.• An interrupt may be sent to the Intel ® 80200processorbaseduponthesettingofbit3intheSDER.When this bit is cleared, the S_RST# signal is deasserted. The software must clear this bit.Developer’s Manual 4-107