Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip7.6.2 Internal Arbitration Control Register - IACR............................................................7-147.6.3 Master Latency Timer Register - MLTR..................................................................7-157.6.4 Multi-Transaction Timer Register - MTTR ..............................................................7-168 Intel ® 80200 Processor based on Intel ® XScale MicroarchitectureCore Interface Unit......................................................................................... 8-18.1 Overview....................................................................................................................................8-18.2 Theory of Operation...................................................................................................................8-28.3 Addressing.................................................................................................................................8-48.4 Internal Bus Commands ............................................................................................................8-58.4.1 ATU Accesses ..........................................................................................................8-58.4.2 Atomic Accesses ......................................................................................................8-58.5 Data Transfers...........................................................................................................................8-68.5.1 Intel ® 80200 Processor Request Bus Read from SDRAM .......................................8-68.5.2 Intel ® 80200 Processor Request Bus Write..............................................................8-88.5.3 Intel ® 80200 Processor Request Bus Read from the Internal Bus .........................8-108.6 Multi-Transaction Timer...........................................................................................................8-128.6.1 Performance Monitoring .........................................................................................8-128.7 Interrupts and Error Conditions................................................................................................8-128.7.1 Master-Abort ...........................................................................................................8-128.7.2 PCI Target-Abort.....................................................................................................8-138.8 Reset Conditions .....................................................................................................................8-138.9 Register Definitions..................................................................................................................8-148.9.1 CIU Interrupt Status Register - CIUISR ..................................................................8-149 DMA Controller Unit ...................................................................................... 9-19.1 Overview....................................................................................................................................9-19.2 Theory of Operation...................................................................................................................9-39.3 DMA Transfer ............................................................................................................................9-49.3.1 Chain Descriptors .....................................................................................................9-59.3.2 Initiating DMA Transfers ...........................................................................................9-89.3.3 Scatter Gather DMA Transfers .................................................................................9-99.3.4 Synchronizing a Program to Chained Transfers.....................................................9-109.3.5 Appending to The End of a Chain...........................................................................9-129.4 64-bit Transfers on a 64-bit PCI Bus .......................................................................................9-139.4.1 64-bit Operation with 64-bit Targets .......................................................................9-139.4.2 64-bit Operation with 32-bit Targets .......................................................................9-139.4.3 64-bit Addressing....................................................................................................9-149.4.4 66 MHz Operation...................................................................................................9-149.5 Data Transfers.........................................................................................................................9-159.5.1 PCI-to-Local Memory Transfers..............................................................................9-159.5.2 Local Memory to PCI Transfers: Memory Write Command ....................................9-159.5.3 Local Memory to PCI Transfers: Memory Write and Invalidate Command.............9-169.5.4 Exclusive Access ....................................................................................................9-169.6 Data Queues............................................................................................................................9-169.7 Data Alignment ........................................................................................................................9-179.7.1 64-bit Unaligned Data Transfers.............................................................................9-179.7.2 64/32-bit Unaligned Data Transfers........................................................................9-189.8 Channel Priority .......................................................................................................................9-189.9 Programming Model State Diagram ........................................................................................9-19Developer’s Manualxi