Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.5.1.1 Disabling the I/O Address Range4.5.1.2 ISA ModeThe I/O address range can be disabled for Primary to Secondary transactions by using either theI/O Enable bit or by using the I/O Base and Limit Registers. When the I/O Limit Register (IOLR) isprogrammed to a value less than the I/O Base Register (IOBR), the Intel ® 80312 I/O companionchip will not forward any transactions from the Primary PCI interface to the Secondary PCIinterface. In this case, all I/O transactions from the Secondary to the Primary will be forwardedupstream through the bridge.The PCI-to-PCI bridge unit of the Intel ® 80312 I/O companion chip implements an ISA Enable bitin the Bridge Control Register (BCR) to provide ISA-awareness for ISA I/O cards on downstreamPCI buses. ISA Mode only affects I/O addresses within the address range defined by the IOBR andIOLR registers. When ISA Mode is enabled by setting the ISA Enable bit in the Bridge ControlRegister (BCR), the bridge will filter out and not forward from Primary to Secondary I/Otransactions with addresses in the upper 768 bytes (300H) of each naturally aligned 1 Kbyte block.Conversely, I/O transactions on the Secondary bus will inversely decode the ISA addresses andtherefore forward I/O transactions with addresses in the upper 768 bytes of each naturally aligned1 Kbyte block from Secondary to Primary.ISA I/O cards only decode the lower 10 bits of the address (1 Kbyte). The upper 768 bytes of the1 Kbyte is assigned for general I/O. Because these cards do not decode the upper 6 bits of the16-bit I/O address, the ISA address is aliased 64 times in the 64 Kbyte I/O address space. Thecombination of ISA addressing modes and the 4 Kbyte I/O address granularity results in an addressdecode that is similar to EISA slot decoding. Devices on the Secondary interface may be mapped tothe first 256 bytes of each 1 Kbyte block. ISA addressing and the ISA Enable bit do not affectordering, posting or error handling behavior of the PCI-to-PCI bridge unit. See Figure 4-5 for anISA address decoding diagram.Figure 4-5.ISA Mode Address DecodePrimaryInterfaceSecondaryInterfaceD00H - FFFHRange Definedby IOBR/IOLRRegister PairC00H - CFFH900H - BFFH800H - 8FFH500H - 7FFH400H - 4FFH100H - 3FFH000H - 0FFH1KbyteBlockDeveloper’s Manual 4-17