Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.6.2 Event Select Register (ESR)The Event Select Register (ESR) controls the specific mode of operation or indicates the currentmode of performance monitoring. There are eight (8) modes supported. To change the monitoredmode, it is necessary to write the entire ESR. The Programmable Event Counters and the GlobalTime Stamp Counter are reset when a new value is written to the ESR. Performance monitoring isdisabled in the default mode.Table 11-6 describes the various monitoring modes and the programmed values for those modes.Table 11-6.Event Select Register (ESR)IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rw rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Processor Local Bus Address0000 1104HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:17 0 Reserved16 0 2PECRx Master Interrupt Enable: When set (1), any/all the programmable event counters interrupts theIntel ® 80312 I/O companion chip on an overflow. When clear (0), none of the programmable eventcounters interrupts the Intel ® 80200 processor on an overflow. In this mode, any counter that has anoverflow condition rolls over to zero and start incrementing.15:3 0 Reserved2:0 0Value in this bit field determines the monitored interface on the Intel ® 80312 I/O companion chip.000 Mode 0 Performance Monitoring Disabled001 Mode 1 Primary PCI Bus & Internal Agents010 Mode 2 Secondary PCI Bus & Internal Agents011 Mode 3 Secondary PCI Bus & PCI Agents100 Mode 4 Secondary PCI Bus & PCI Agents (external masters 3..5)101 Mode 5 Intel ® 80312 I/O companion chip internal bus, DMA Channels & AA110 Mode 6 Intel ® 80312 I/O companion chip internal bus, PATU, SATU & Intel ® 80312 I/Ocompanion chip111 Mode 7 Intel ® 80312 I/O companion chip internal bus, PCI buses (primary & secondary)11-24 Developer’s Manual
Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.6.3 Event Monitoring Interrupt Status Register (EMISR)Note:The Event Monitoring Interrupt Status Register (EMISR) generates interrupts to the Intel ® 80312I/O companion chip. Bits 14:0 when set indicate an overflow condition in either the Global TimeStamp Counter or the Programmable Event Counters. This generates an interrupt on the FIQ# pinof the Intel ® 80200 processor. Bits 14:0 can only be set by the Event Counters and/or the GlobalTime Stamp Counter and can only be cleared by the Intel ® 80200 processor.When this register is read by the Intel ® 80200 processor and multiple bits are set, it is theresponsibility of the application software to record the value and prioritize the sequence of actions.Any bit (bits 14:0) once set is cleared by writing a 1 to the specific bit field.It is the responsibility of the application software to clear the individual bit fields in the registeronce a new mode is programmed into the ESR.Table 11-7. Event Monitoring Interrupt Status Register (EMISR) (Sheet 1 of 2)IOPAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrcrcrcrcrcrcrcrcrcrcrcrcrcrcrcPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na31 28 24 20 16 12 8 4 0Intel ® 80200 Processor Local Bus AddressAttribute Legend: RW = Read/Write0000 1108HRV = Reserved RC = Read ClearPR = Preserved RO = Read OnlyRS = Read/Set NA = Not AccessibleBit Default Description31:15 0 Reserved14 0 2Bit value indicates status of the Programmable Event Counter 14 (PEC14) during event monitoring.When clear (0), no PEC14 overflow interrupt is pending. When set (1), a PEC14 overflow interrupt ispending.13 0 2Bit value indicates the status of the Programmable Event Counter 13 (PEC13) during event monitoring.When clear (0), no PEC13 overflow interrupt is pending. When set (1), a PEC13 overflow interrupt ispending.12 0 2Bit value indicates the status of the Programmable Event Counter 12 (PEC12) during event monitoring.When clear (0), no PEC12 overflow interrupt is pending. When set (1), a PEC12 overflow interrupt ispending.11 0 2Bit value indicates the status of the Programmable Event Counter 11 (PEC11) during event monitoring.When clear (0), no PEC11 overflow interrupt is pending. When set (1), a PEC11 overflow interrupt ispending.10 0 2Bit value indicates the status of the Programmable Event Counter 10 (PEC10) during event monitoring.When clear (0), no PEC10 overflow interrupt is pending. When set (1), a PEC10 overflow interrupt ispending.9 0 2Bit value indicates the status of the Programmable Event Counter 9 (PEC9) during event monitoring.When clear (0), no PEC9 overflow interrupt is pending. When set (1), a PEC9 overflow interrupt ispending.8 0 2Bit value indicates the status of the Programmable Event Counter 8 (PEC8) during event monitoring.When clear (0), no PEC8 overflow interrupt is pending. When set (1), a PEC8 overflow interrupt ispending.Developer’s Manual 11-25
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Memory Controller 3This chapter des
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