Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.3.6 Slave OperationsTable 12-6 describes the I 2 C Bus Interface Unit’s responsibilities as a slave device.Table 12-6.Slave TransactionsI 2 CSlaveActionMode ofOperationDefinitionSlave-receive(default mode)Setting the SlaveAddress DetectedbitReadonebyteofI 2 C Data from theIDBRTransmitAcknowledge tomaster-transmitterWrite one byte ofI 2 C data to theIDBRWait forAcknowledgefrommaster-receiverSlave-receiveonlySlave-receiveSlave-transmitSlave-receiveonlySlave-receiveonlySlave-transmitonlySlave-transmitonly• I 2 C Bus Interface Unit monitors all slave address transactions.• The I 2 C Bus Interface Unit Enable bit must be set.• I 2 C Bus Interface Unit monitors bus for START conditions. When aSTART is detected, the interface reads the first 8 bits and comparesthe most significant 7 bits with the 7 bit I 2 C Slave Address Registerand the General Call address (00H). When there is a match, the I 2 CBus Interface Unit sends an Ack.• When the first 8 bits are all zero’s, this is a general call address.When the General Call Disable bit is clear, both the General CallAddress Detected bit and the Slave Mode Operation bit in the ISR isset. See Section 12.3.7.• When the 8th bit of the first byte (R/W# bit) is low, the I 2 CBusInterfaceUnitstaysinslave-receivemodeandtheSlaveModeOperation bit is cleared. When the R/W# bit is high, the I 2 CBusInterface Unit transitions to slave-transmit mode and the Slave ModeOperation bit is set.• Indicates the interface has detected an I 2 C operation that addressesthe Intel ® 80200 processor (this includes general call address). TheIntel ® 80200 processor can distinguish an ISAR match from aGeneral Call by reading the General Call Address Detected bit.• An interrupt is signalled (when enabled) after the matching slaveaddress is received and acknowledged.• Data receive mode of I 2 C slave operation.• Eight bits are read from the serial bus into the shift register. When afull byte has been received and the Ack/Nack bit has completed, thebyte is transferred from the shift register to the IDBR.• Occurs when the IDBR Receive Full bit in the ISR is set and theTransfer Byte bit is clear. When enabled, the IDBR Receive FullInterrupt is signalled to the Intel ® 80200 processor.• Intel ® 80200 processor reads 1 data byte from the IDBR. When theIDBR is read, the Intel ® 80200 processor writes the desiredAck/Nack Control bit and set the Transfer Byte bit. This causes theI 2 C Bus Interface Unit to stop inserting wait states and let the mastertransmitter write the next piece of information.• As a slave-receiver, the I 2 C Bus Interface Unit is responsible forpulling the SDA line low to generate the Ack pulse during the highSCL period.• The Ack/Nack Control bit controls the Ack data the I 2 CBusInterfaceUnit drives. See Section 12.3.3.• Data transmit mode of I 2 C slave operation.• Occurs when the IDBR Transmit Empty bit is set and the TransferByte bit is clear. When enabled, the IDBR Transmit Empty Interrupt issignalled to the Intel ® 80200 processor.• Intel ® 80200 processor writes a data byte to the IDBR and set theTransfer Byte bit to initiate the transfer.• As a slave-transmitter, the I 2 C Bus Interface Unit is responsible forreleasing the SDA line to allow the master-receiver to pull the linelow for the Ack.• See Section 12.3.3.12-18 Developer’s Manual
Intel ® 80312 I/O Companion ChipI 2 C Bus Interface UnitFigure 12-12 through Figure 12-14 are examples of I 2 C transactions. These show the relationshipsbetween master and slave devices.Figure 12-12. Master-Transmitter Write to Slave-ReceiverSTARTSlave AddressR/W#0ACKDataByteACKDataByteACKSTOPFirst ByteWriteNBytes+ACKMaster to SlaveSlavetoMasterFigure 12-13. Master-Receiver Read to Slave-TransmitterSTARTSlave AddressR/W#1ACKDataByteACKDataByteACK#STOPMaster to SlaveFirst ByteReadSlavetoMasterDefaultSlave-ReceiveModeNBytes+ACKFigure 12-14. Master-Receiver Read to Slave-Transmitter, Repeated START, Master-TransmitterWrite to Slave-ReceiverSTARTSlaveAddressR/W#1ACKDataByteACKDataByteACKSRSlave R/W#Address 0ACKDataByteACKDataByteACKSTOPReadNBytes+ACKRepeatedSTARTData ChainingWriteNBytes+ACKMaster to SlaveSlavetoMasterDeveloper’s Manual 12-19
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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