Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.14.9.1 PCI Commands SupportThe Memory Write and Invalidate command is fully supported by all channels of the DMAcontroller. Refer to Section 9.5.3, “Local Memory to PCI Transfers: Memory Write and InvalidateCommand” on page 9-16 for a complete description of the behavior of the DMA channel duringthis PCI bus cycle.Table 9-13.PCI CommandsC/BE[3:0]# PCI Command Type Description0000 2 Intack Not Supported0001 2 SpCyc Not Supported0010 2 I/O Read Not Supported0011 2 I/O Write Not Supported0100 2 reserved Not Supported0101 2 reserved Not Supported0110 2 Memory Read Memory Read of less than one cacheline0111 2 Memory Write Memory Write1000 2 reserved Not Supported1001 2 reserved Not Supported1010 2 Configuration Read Not Supported1011 2 Configuration Write Not Supported1100 2 Memory Read Multiple Memory Read of more than one cacheline1101 2 reserved Not Supported1110 2 Memory Read Line Memory Read of one cacheline1111 2Memory Write andInvalidateMemory Write which guarantees the transfer of complete cacheline (s) during the current transaction9-36 Developer’s Manual