Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80312 I/O Companion Chip Arbitration7.4.2 Internal Master Latency TimerAll the internal bus masters use a common Internal Master Latency Timer (IMLT). After the IMLTexpires, the current internal bus master must relinquish the bus when the arbiter deasserts itsGNT#. The 12-bit IMLT is preloaded with the value programmed into the MLTR.7.5 Reset ConditionsTable 7-5 shows all the arbitration blocks and the signal responsible for resetting its logic:Table 7-5.Arbitration Block and Reset SignalsArbitration BlockSecondary Arbiter (SARB)Internal Arbiter (IARB)Primary PCI Selector (PSEL)Primary Master Latency TimerSecondary Master Latency TimerReset With:S_RST#P_RST#P_RST#P_RST#S_RST#When the secondary bus is reset with S_RST#, the SARB logic is reset which effectively moves allsecondary PCI devices to their programmed priority levels and starts the round robin arbitrationsequence on the lowest number device at each priority level. Similarly, I_RST# moves all theinternal agents to their programmed priority levels and starts the round robin arbitration sequenceon the lowest number device at each priority level.Because the SACR is located in the bridge configuration register space, it is reset when P_RST# isasserted. Refer to Section 7.6.1, “Secondary Arbitration Control Register - SACR” on page 7-13for its value during reset.7.5.1 S_REQ64# ControlWhile P_RST# is asserted, the SARB samples the 32BITPCI_EN# pin. The SARB uses thesampled value to drive S_REQ64# while S_RST# is asserted.• If 32BITPCI_EN# is deasserted while P_RST# is asserted, S_REQ64# is asserted during theassertion of S_RST#. After the deassertion of S_RST#, S_REQ64# is driven high(deasserted) for one to two clocks before floating the S_REQ64# pin.• If 32BITPCI_EN# is asserted while P_RST# is asserted, S_REQ64# floats to allow themotherboard to pull-up.S_REQ64# remains valid for one clock (P_CLK) afterS_RST# deasserts.Developer’s Manual 7-11