Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.25 Primary Bridge Interrupt Status Register - PBISRThe Primary Bridge Interrupt Status Register notifies the Intel ® 80200 processor of the source of aPrimary Bridge interface interrupt. In addition, this register is written to clear the source of theinterrupt to the interrupt unit of the Intel ® 80312 I/O companion chip (see Section 2.3, “Intel ®80312 I/O Companion Chip Interrupts” on page 2-2). All bits in this register are Read Only fromPCI and Read/Clear from the local bus.Bits 5:0 are a direct reflection of bits 15:11 and bit 8 (respectively) of the Primary Status Register(these bits are set at the same time by hardware but need to be cleared independently). Theconditions that result in a Primary Bridge interrupt to the Intel ® 80200 processor are cleared bywriting a “1” to the appropriate bits in this register.The individual setting of the bits within the PBISR can be masked through the bits 10:6, bit 4 andbit 1 of the SDER. Refer to Section 4.15.34 for details.Table 4-48.Primary Bridge Interrupt Status Register - PBISRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc rc rc rc rcPCIAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrcrcrcrcrcrcrcPCI Configuration Offset44 - 47HIntel ® 80200 Processor Local Bus Address0000 1044HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:07 0000000H Reserved.06 0 2 is written to transition the Bridge function Power State from either D3 to D0 or D0 to D3 and the PowerPower State Transition - When the Power State Field of the Power Management Control/Status RegisterState Transition Interrupt mask is cleared, this bit is set.Detected Parity Error - This bit is set when a parity error is detected during a data transfer on the Primarybus even when parity handling is disabled. Set under the following conditions:• Write Data Parity Error when the Primary interface of the Bridge is a slave (downstream write).05 0 2• Read Data Parity Error when the Primary interface of the Bridge is a master (upstream read).• Any Address Parity Error on the Primary Bus (including one generated by the Primary interface ofthe Bridge).04 0 2 P_SERR# Asserted - This bit is set when P_SERR# is asserted on the Primary PCI bus.PCI Master Abort - This bit is set whenever a transaction initiated by the Primary master interface ends03 0 2 in a Master-Abort.PCI Target Abort (Master) - This bit is set whenever a transaction initiated by the Primary master02 0 2 interface ends in a Target-Abort.PCI Target Abort (Target) - This bit is set whenever the Primary interface, acting as a target, terminates01 0 2 the transaction on the PCI bus with a Target-Abort.00 0 21. the bus agent asserted P_PERR# itself or observed P_PERR# asserted2. the agent setting the bit acted as the bus master for the operation in which the error occurredPCI Master Parity Error - The Primary interface sets this bit when three conditions are met:3. the Parity Checking Enable bit (PCR Register) is setDeveloper’s Manual 4-113