Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-47. Secondary IDSEL Select Register - SISR (Sheet 2 of 2)IOPAttributes15 12 8 4 0rv rv rv rv rv rv rw rw rw rw rw rw rw rw rw rwPCIAttributesrvrvrvrvrvrvrw rw rw rw rw rwrw rw rw rwPCI Configuration Offset42 - 43HIntel ® 80200 Processor Local Bus Address0000 1042HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description02 0 2AD23 - IDSEL Disable - When this bit is set, AD23 will be deasserted for any possible Type 1 to Type 0conversion. When clear, AD23 will be asserted when Primary addresses AD[15:11] =00111 2 during aType1toType0conversion.01 0 2AD24- IDSEL Disable - When this bit is set, AD24 will be deasserted for any possible Type 1 to Type 0conversion. When clear, AD24 will be asserted when Primary addresses AD[15:11] = 01000 2 during aType1toType0conversion.00 0 2AD25- IDSEL Disable - When this bit is set, AD25 will be deasserted for any possible Type 1 to Type 0conversion. When clear, AD25 will be asserted when Primary addresses AD[15:11] = 01001 2 during aType1toType0conversion.4-112 Developer’s Manual