Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging UnitEach circular queue has a head pointer and a tail pointer. The pointers are offsets from the QueueBase Address. Writes to a queue occur at the head of the queue and reads occur from the tail. Thehead and tail pointers are incremented by either the Intel ® 80200 processor or the Messaging Unithardware. Which unit maintains the pointer is determined by the writer of the queue. More detailsabout the pointers are given in the queue descriptions below. The pointers are incremented after thequeue access. Both pointers wrap around to the first address of the circular queue when they reachthe circular queue size.The Messaging Unit generates an interrupt to the Intel ® 80200 processor or generate a PCIinterrupt under certain conditions. In general, when a Post queue is written, an interrupt isgenerated to notify the receiver that a message was posted.The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).All four queues must be the same size and may be contiguous. Therefore, the total amount of localmemory needed by the circular queues ranges from 64 Kbytes to 1 Mbyte. The Queue size isdetermined by the Queue Size field in the MU Configuration Register.There is one base address for all four queues. It is stored in the Queue Base Address Register (QBAR).The starting addresses of each queue is based on the Queue Base Address and the Queue Size field.Table 6-4 shows an example of how the circular queues should be set up based on the Intelligent I/O(I 2 O) Architecture Specification. Other ordering of the circular queues is possible, however.Table 6-4.Queue Starting AddressesQueueInbound Free QueueInbound Post QueueOutbound Post QueueOutbound Free QueueStarting AddressQBARQBAR + Queue SizeQBAR + 2 * Queue SizeQBAR + 3 * Queue SizeDeveloper’s Manual 6-9