Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.38 Primary ATU Interrupt Status Register - PATUISRThe Primary ATU Interrupt Status Register is used to notify the Intel ® 80200 processor of thesource of a Primary ATU interrupt. In addition, this register is written to clear the source of theinterrupt to the interrupt unit of the Intel ® 80312 I/O companion chip. All bits in this register areRead/Clear.Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the Primary ATU StatusRegister (these bits are set at the same time by hardware but need to be cleared independently). Bit7 is set by an error associated with the internal bus of the Intel ® 80312 I/O companion chip. Theconditions that result in a Primary ATU interrupt are cleared by writing a 1 to the appropriate bits inthis register.Note that bits 4:0, bits 12:11, bit 9 and bit 7 can result in an IRQ# interruptbeingdriventotheIntel ® 80200 processor.Table 5-66. Primary ATU Interrupt Status Register - PATUISR (Sheet 1 of 2)IOPAttributesrv31rvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc rv rc rv rv rc rc rc rc rcPCIAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrorororvrorvrvrororororoIntel ® 80200 Processor Local Bus Address1290HPCI Configuration Address Offset90H - 93HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 00000H Reserved11 0 2Power State Transition - When the Power State Field of the ATU Power Management Control/StatusRegisteriswrittentotransitiontheATUfunctionPowerStatefromeitherD3toD0orD0toD3andtheATU Power State Transition Interrupt mask bit is cleared, this bit is set.10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the primary ATU.09 0 2• Read Data Parity Error when the PATU is a master (outbound read). Read Data Parity Errors whenDMA Channel 0 or DMA Channel 1 is the master ARE NOT logged here, and instead are logged inDetected Parity Error - set when a parity error is detected on the primary PCI bus even when thePATUCMD register’s Parity Error Response bit is cleared. Set under the following conditions:• Write Data Parity Error when the PATU is a slave (inbound write).the appropriate DMA CSR.• Any Address Parity Error on the Primary Bus (including one generated by the PATU or DMAChannels 0 & 1 when loopback is enabled).08 0 2 ReservedInternal Bus Master Abort - set when a transaction initiated by the ATU internal bus master interface07 0 2 ends in a Master-abort.06:05 00 2 Reserved.04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the primary ATU.PCI Master Abort - set when a transaction initiated by the ATU PCI master interface ends in a03 0 2 Master-abort.5-100 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI Address Translation UnitTable 5-66. Primary ATU Interrupt Status Register - PATUISR (Sheet 2 of 2)IOPAttributesrv31rvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc rv rc rv rv rc rc rc rc rcPCIAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrorororvrorvrvrororororoIntel ® 80200 Processor Local Bus Address1290HPCI Configuration Address Offset90H - 93HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default DescriptionPCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a02 0 2 Target-abort.PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on01 0 2 the PCI bus with a target abort.PCI Master Parity Error - The ATU interface sets this bit when three conditions are met:• the PATU asserted S_PERR# or observed S_PERR# asserted00 0 2• the PATU acted as the bus master for the operation in which the error occurred• Parity Error Response bit is set (in the Primary ATU Command Register)Developer’s Manual 5-101
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