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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>PCI-to-PCI Bridge UnitThe target PCI interface will initiate the read transaction with the PCI address and command usedon the initiating bus and then put the return data into a DRC Queue to return it to the initiating PCIbus. The data flow is summarized in the following statements:• The bridge PCI master interface on the target bus will request the PCI bus when an readrequest address is written to a Transaction Queue.• Once the bus is granted to the bridge interface for the read transaction, the target bus masterinterface will initiate a read transaction with the same address and command used on theinitiating interface. When the read is a memory read (and a 64-bit bus is enabled) the bridgewill assert REQ64# attempting to use 64-bit data phases. When the bus is not 64-bit enabledor it is an I/O or Configuration Read, REQ64# is not asserted.• When the transaction is claimed and retried, the bus interface will re-attempt the transaction.When the master interface receives a master-abort, a master-abort condition is loaded into theDRC Queue for return to the master on the initiating bus. The condition loaded is dependenton the Master Abort bit in the BCR. See Section 4.10.1.4 for details.• Once the read transaction is claimed, the bridge master interface will read data from the PCItarget. When ACK64# is asserted data is read 64-bits at a time. When ACK64# is not asserted,data is read 32-bits at a time.• The master interface will continue to read data until one of the following is true:— The prefetch amount of DWORDs specified in Table 4-12 is reached.— The target disconnects the transaction.— A PCI time-out occurs.— The target performs a target-abort (this condition is returned and loaded into the DRCQueue).— The bridge master interface encounters a 4 Kbyte boundary.• When parity checking is enabled and a data parity error is detected, the master interface willassert PERR# and continue reading data until one of the previous conditions is true.4-56 Developer’s Manual

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