Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-21. SSR Error Reporting Summary (Sheet 1 of 2)Error Bit in Primary StatusRegister (SSR)Error ConditionQualifying Bit in PrimaryCommand Register(BCR)Detected Parity Error - Bit 15Data Parity Error Detected - Bit 8Received System Error - bit 14Master Abort - bit 13Target Abort (master) - bit 12Address Parity Error on SecondaryInterfaceDownstream Read Data ParityError on Secondary BusUpstream Posted Memory WriteData Parity Error on SecondaryBusUpstream Delayed Write DataParity Error During Request Cycleon Secondary Bus when Requestis Seen with Bad Parity &Immediately CompletedUpstream Delayed Write DataParity Error During CompletionCycle on Secondary Bus, Onlywhen Error Occurred DuringRequest Phase of Transaction onSecondary Bus and CompletionRequest from Master MatchesInitial Request ErrorDownstream Delayed Read DataParity Error on Secondary BusDownstream Delayed Write DataParity Error During CompletionCycle on Secondary BusDownstream Posted Memory WriteData Parity Error on the SecondaryBusS_SERR# Detected on SecondaryInterfaceAddress Parity Error on SecondaryInterfaceDownstream Delayed Read(memoryorI/O)WhichReceivedaMaster Abort on the SecondaryBusDownstream Write (posted ordelayed) Which Received a MasterAbort on the Secondary BusDownstream Delayed Read(memoryorI/O)WhichReceivedaTarget Abort on the Secondary BusDownstream Write (posted ordelayed) Which Received a TargetAbort on the Secondary BusN/AN/AN/ASecondary Parity Error ResponseEnable must be SET- bit 0Secondary Parity Error ResponseEnable must be CLEAR- bit 0Secondary Parity Error ResponseEnable - bit 0Secondary Parity Error ResponseEnable - bit 0Secondary Parity Error ResponseEnable - bit 0N/ASecondary Parity Error ResponseEnable - bit 0 (BCR)N/AN/AN/AN/ADeveloper’s Manual 4-77