Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipTest Features14.1.4 TAP Test Data RegistersThe Intel ® 80312 I/O companion chip contains three test data registers (device identification,bypass, and boundary-scan). Each test data register selected by the TAP controller is connectedserially between TDI and TDO. TDI is connected to the test data register most significant bit. TDOis connected to the least significant bit. Data is shifted one bit position within the register towardsTDO on each rising edge of TCK. While any register is selected, data is transferred from TDI toTDO without inversion. The following sections describe each of the test data registers. SeeFigure 14-5 for an example of loading the data register.14.1.4.1 Device Identification RegisterThe device identification register is a 32-bit register containing the manufacturer identificationcode, part number code, version code and other information in the format shown in the Intel ®80312 I/O companion chip data sheet. The identification register is selected only by the idcodeinstruction. When the TAP controller Test_Logic_Reset state is entered, idcode is asynchronouslyloaded into the instruction register. The device identification register loads the fixed parallel inputvalue in the Capture_DR state.14.1.4.2 Bypass RegisterThe required bypass register, a one-bit shift register, provides the shortest path between TDI andTDO when a bypass instruction is in effect. This allows rapid movement of test data to and fromother components on the board. This path can be selected when no test operation is beingperformed on the processor.14.1.4.3 Boundary-Scan RegisterThe boundary-scan register contains a cell for each pin as well as control cells for I/O and theHIGHZ pin.Table 14-4 shows the bit order of the Intel ® 80312 I/O companion chip boundary-scan register. Alltable cells that contain “Control” select the direction of bidirectional pins or HIGHZ output pins.When a “0” is loaded into the control cell, the associated pin(s) are HIGHZ or selected as input.The boundary-scan register is a required set of serial-shiftable register cells, configured inmaster/slave stages and connected between each of the Intel ® 80312 I/O companion chip pins andon-chip system logic. The V CC ,V SS and JTAG pins are NOT in the boundary-scan chain.The boundary-scan register cells are dedicated logic and do not have any system function. Datamay be loaded into the boundary-scan register master cells from the device input pins and outputpin-drivers in parallel by the mandatory sample/preload and extest instructions. Parallel loadingtakes place on the rising edge of TCK in the Capture_DR state.Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clockedby the rising edge of TCK in the Shift_DR state. When the required data has been loaded into themaster-cell stages, it can be driven into the system logic at input pins or onto the output pins on thefalling edge of TCK in the Update_DR state. Data may also be shifted out of the boundary-scanregister by means of the TDO serial output pin at the falling edge of TCK.Developer’s Manual 14-5