Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory ControllerExample 3-7. Write Page MissA write that misses the open pages encounters a miss penalty because the currently open pageneeds to be closed before the MCU can issue the write to the SDRAM. Closing a page meansissuing a precharge command to the row that needs to be closed. Figure 3-14 illustrates a writemiss. The new page and the old page are in bank 0.Figure 3-14.SDRAM Write, 40 bytes, ECC Enabled, BL=4, Page MissSCLK0 1 2 3 4 5 6 7 8 9 10 111213SCE[0]#SRAS#NewRowSCAS#SWE#SA[12:0]ROW COL COL+4DQ[71:0]D 0 D 1 D 2 D 3 D 4SDQM[7:0] 00FFAddressDecode(Miss)PrechargeT rpT rcdGenerateECC• Once an external master starts a transaction, the MCU decodes the address to determine whenthe transaction should be claimed.— When the address falls in the MCU address range, the MCU claims the transaction.• In the following cycle, the MCU closes the currently open page by issuing a prechargecommand to the currently open row.—TheMCUwaitsT rp (3) cycles after the precharge command before the MCU issues therow-activate command for the new write transaction.• The MCU issues the row-activate command enabling the appropriate row.— The MCU asserts SRAS# while driving the row address on SA[12:0].• After T rcd (2) cycles, the MCU issues the write command by asserting SCAS# and driving thecolumn address on SA[12:0].The remainder of the write transaction is identical to “Write Page Hit” on page 3-24.Developer’s Manual 3-25