Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.2 Claiming a PCI TransactionIn general, the PCI-to-PCI bridge unit, as a target on the initiating bus, uses medium timing toassert DEVSEL# to claim a bus transaction.However, when the bridge Special Memory Window is enabled (see Section 4.5.4.1, “SpecialExternal Hot-Plug Unit Decode” on page 4-21), the bridge could claim cycles in this window onlywith Slow decode timing.With the exception of Primary Interface Slow Decode under certain, special conditions, theperformance of the bridge will not be affected. Both Slow and Medium Decode timings will meetthe PCI specification of claiming a transaction within five clocks of the assertion of FRAME# bythe initiating PCI device. The bridge target interface will claim the transaction depending on thetransaction type and address. See the rules for address decoding for memory and I/O transactions inSection 4.5 and for configuration transactions in Section 4.4.The bridge unit, as a master on the target bus, expects DEVSEL# to be asserted from the targetdevice within five PCI clocks of asserting FRAME#. When the target interface does not receiveDEVSEL# within the required amount of time, it will signal a Master-Abort on the target bus whenthe function is enabled (see Section 4.10.1 for Master-Abort information).See the PCI Local Bus Specification, Revision 2.2 for full details on transaction claiming.4.6.2.1 Latency TimersA latency timer (LT) is used to create a mechanism that limits one masters ownership of a PCI busin the presence of other bus masters. There are two latency timers in the bridge, one for each of thePCI interface masters.The function of each latency timer is defined as:• A LT is initialized and suspended (not counting) whenever a master interface (Primary orSecondary) is not asserting FRAME#.• When a master interface asserts FRAME#, the LT will start counting down one for every PCIclock cycle that FRAME# is asserted.• When the master interface deasserts FRAME# before the LT has expired (reached zero), theLT is meaningless to the transaction. The LT is initialized when FRAME# is deasserted.• When the LT expires before the transaction completes, the interface must relinquish the busand terminate the transaction (see Section 4.10.1) as soon as the master interface GNT# signalis deasserted. When the LT expires and the master interface GNT# signal is still asserted, thetransaction is allowed to continue until it is complete or the master GNT# signal is deasserted.The exception to this rule is when a master is currently performing a Memory Write andInvalidate command on the bus. Refer to Section 4.10.1.3 for details.In essence, the LT creates a minimum time slice that each master is allowed to own the PCI bus.Two registers exist within the bridge unit configuration space which define the maximum countand granularity of both the Primary and Secondary latency timers; the Primary Latency TimerRegister (PLTR) and the Secondary Latency Timer Register (SLTR). Each register is 8 bits wideresultinginatimesliceofupto248PCIclocksthateachinterfacecanownitsrespectivePCIbus.The lower three bits (02 through 00) of the PLTR and the SLTR are hardwired to 000 2 which forcesa minimum granularity for the timer of eight PCI clocks. The upper five bits of the register areprogrammable to allow the timer value for each PCI interface to be independently programmed to avalue between 11111000 2 and 00000000 2 resulting in timer count of anywhere from 0 to 248.Developer’s Manual 4-29