Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip15.1.1 Clocking Theory of Operation .................................................................................15-215.1.2 Clocking Region 1...................................................................................................15-215.1.3 Clocking Region 2...................................................................................................15-215.1.4 Clocking Region 3...................................................................................................15-315.1.5 Clocking Region 4...................................................................................................15-315.1.6 Output Clocks .........................................................................................................15-315.1.7 Clocking Region Summary .....................................................................................15-415.2 Reset Overview .......................................................................................................................15-515.2.1 Primary PCI Reset ..................................................................................................15-615.2.2 Secondary PCI Reset .............................................................................................15-715.2.3 Internal Bus Reset ................................................................................................15-1115.3 Reset Strapping Options........................................................................................................15-1315.3.1 Secondary PCI Bus Arbitration Unit......................................................................15-1415.3.2 Internal Bus Arbitration Unit..................................................................................15-1415.3.3 Reset State Operation ..........................................................................................15-1415.4 Initialization Overview............................................................................................................15-1515.4.1 Initialization Modes ...............................................................................................15-1515.4.2 Mode 0 Initialization ..............................................................................................15-1615.4.3 Mode 1 Initialization ..............................................................................................15-1615.4.4 Mode 2 Initialization ..............................................................................................15-1615.4.5 Mode 3 (Default Mode) .........................................................................................15-16APeripheral Memory-Mapped Registers ........................................................A-1A.1 Overview................................................................................................................................... A-1A.2 Accessing the Peripheral Memory-Mapped Registers.............................................................. A-2A.3 Architecturally Reserved Memory Space.................................................................................. A-3A.4 Peripheral Memory-Mapped Register Address Space ............................................................. A-4Developer’s Manualxvii