Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.22 Secondary Inbound ATU Base Address Register - SIABARThe Secondary Inbound ATU Base Address Register (SIABAR) defines the block of memoryaddresses where the secondary inbound translation window begins. The inbound ATU decodes andforwards the bus request to the Intel ® 80312 I/O companion chip internal bus with a translatedaddress to map into the Intel ® 80312 I/O companion chip internal memory. The SIABAR definesthe base address and describes the required memory block size; see Section 5.7.15, “DeterminingBlock Sizes for Base Address Registers” on page 5-76. Bits 31 through 12 of the SIABAR is eitherread/write bits or read only with a value of 0 depending on the value located within the SIALR.This configuration allows the SIABAR to be programmed per PCI Local Bus Specification,Revision 2.2.The base address register’s programmed value must comply with the PCI programmingrequirements for address alignment. Refer to the PCI Local Bus Specification, Revision 2.2 foradditional information on programming base address registers.Note:Table 5-50.When trying to access the Messaging Unit from the Secondary PCI bus through the Bridge (seeSection 5.7.37, “ATU Configuration Register - ATUCR” on page 5-98, Secondary Bus MessagingUnit Access Enable Bit), the SIABAR must be programmed the same as the PIABAR.Secondary Inbound ATU Base Address Register - SIABARIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv ro ro ro roPCIAttributesrwrw rw rw rw rw rw rwrw rw rw rw rw rw rw rwrw rw rw rwrvrvrvrvrvrvrvrvrorororoIntel ® 80200 Processor Local Bus Address1248HPCI Configuration Address Offset48H - 4BHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 00000HSecondary Translation Base Address - These bits define the actual location to which the SecondaryTranslation function responds when addressed from the secondary PCI bus. The default block size isindeterminate.11:04 00H Reserved.03 1 2 Prefetchable Indicator - This bit defines the memory spaces as prefetchable.Address Type - These bits define where the block of memory can be located. The base address must be02:01 00 2 located anywhere in the first 4 Gbyte of address space (lower 32-bits of address).Memory Space Indicator - This bit shows the register contents describes memory or I/O space base00 0 2 address. The ATU does not occupy I/O space; thus, this bit must be zero.Developer’s Manual 5-83