Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface UnitFigure 12-3 shows the relationship between the SDA and SCL lines for a START and STOPcondition.Figure 12-3.Start and Stop ConditionsSDASCL~ ~ ~Start ConditionStop Condition12.2.3.1 START ConditionThe START condition (bits 1:0 of the ICR set to 01 2 ) initiates a master transaction or repeatedSTART. Software must load the target slave address and the R/W# bit in the IDBR (seeSection 12.8.4, “I 2 C Data Buffer Register- IDBR” on page 12-33) before setting the START ICRbit. The START and the IDBR contents are transmitted on the I 2 C bus when the ICR Transfer Bytebit is set. The I 2 C bus stays in master-transmit mode when a write is requested or entersmaster-receive mode when a read is requested. For a repeated start (a change in read or write or achange in the target slave address), the IDBR contains the updated target slave address and theR/W# bit. A repeated start enables multiple transfers to different slaves without giving up the bus.The START condition is not cleared by the I 2 C unit. When arbitration is lost while initiating aSTART, the I 2 C unit may re-attempt the START when the bus becomes free. See Section 12.3.4,“Arbitration” on page 12-12 for details on how the I 2 C unit functions under those circumstances.12.2.3.2 No START or STOP ConditionNo START or STOP condition (bits 1:0 of the ICR set to 00 2 ) is used in master-transmit modewhile the Intel ® 80200 processor is transmitting multiple data bytes (see Figure 12-3). Softwarewrites the data byte, sets the IDBR Transmit Empty bit in the ISR (and interrupt when enabled),and clears the Transfer Byte bit in the ICR. The software then writes a new byte to the IDBR andsets the Transfer Byte ICR bit, which initiates the new byte transmission. This continues until thesoftware sets the START or STOP bit. The START and STOP bits in the ICR are not automaticallycleared by the I 2 C unit after the transmission of a START, STOP or repeated START.After each byte transfer (including the Ack/Nack bit) the I 2 C unit holds the SCL line low (insertingwait states) until the Transfer Byte bit in the ICR is set. This action notifies the I 2 C unit to releasethe SCL line and allow the next information transfer to proceed.12-6 Developer’s Manual