Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface UnitTable 12-9. I 2 C Control Register - ICR (Sheet 3 of 3)IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address1680HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description01 0 2STOP: usedtoinitiateaSTOPconditionaftertransferringthenextdatabyteontheI 2 C bus when inmaster mode. In master-receive mode, the Ack/Nack control bit must be set in conjunction with this bit.See Section 12.2.3.3, “STOP Condition” on page 12-7 for more details on the STOP state.0= DonotsendaSTOP.1= SendaSTOP.00 0 2“START Condition” on page 12-6 for more details on the START state.0= DonotsendaSTART.START: usedtoinitiateaSTARTconditiontotheI 2 C unit when in master mode. See Section 12.2.3.1,1= SendaSTART.Developer’s Manual 12-29