Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.6.7 ATU Error SummaryTable 5-22 through Table 5-25 summarize the ATU error reporting for PCI bus errors (Table 5-22and Table 5-23) and internal bus errors (Table 5-24 and Table 5-25). The tables assume that allerror reporting is enabled through the appropriate command registers (unless otherwise noted). ThePrimary and Secondary ATU Status Registers record PCI bus errors. Note that the SERR#Asserted bit in the Status Register is set only when the SERR# Enable bit in the CommandRegister is set. The Primary and Secondary ATU Interrupt Status Registers record Intel ® 80200processor interrupt status information.Note:Table 5-22.When an external agent violates PCI protocol, Primary and Secondary ATU behavior may beunpredictable/undefined.Primary ATU Error Reporting Summary - PCI InterfaceErrorConditionInbound WriteAddress ParityErrorInbound WriteData ParityErrorInbound WriteMaster or TargetAbortInbound ReadAddress ParityErrorInbound ReadData ParityErrorInbound ReadTarget AbortOutbound WriteMaster AbortOutbound WriteData ParityErrorOutbound WriteTarget AbortOutbound ReadMaster AbortOutbound ReadData ParityErrorOutbound ReadTarget AbortP_SERR#DetectedBits Set inPrimary ATU Status Register(PATUSR)Bits Set inPrimary ATU Interrupt StatusRegister (PATUISR)Interrupt Mask Bit inPATUIMR or ATUCRDetected Parity Error - bit 15 Detected Parity Error - bit 9 PATUIMR bit 7P_SERR# Asserted - bit 14 P_SERR# Asserted - bit 10 PATUIMR bit 6N/A P_SERR# Detected - bit 4 ATUCR bit 9Detected Parity Error - bit 15 Detected Parity Error - bit 9 PATUIMR bit 7P_SERR# Asserted - bit 14 P_SERR# Asserted - bit 10 PATUIMR bit 6N/A P_SERR# Detected - bit 4 ATUCR bit 9Detected Parity Error - bit 15 Detected Parity Error - bit 9 PATUIMR bit 7P_SERR# Asserted - bit 14 P_SERR# Asserted - bit 10 PATUIMR bit 6N/A P_SERR# Detected - bit 4 ATUCR bit 9N/A N/A N/ATarget Abort (target) - bit 11 PCI Target Abort (target) - bit 1 PATUIMR bit 3Master Abort - bit 13 PCI Master Abort - bit 3 PATUIMR bit 5Master Parity Error - bit 8 PCI Master Parity Error - bit 0 PATUIMR bit 2Target Abort (master) - bit 12 PCI Target Abort (master) - bit 2 PATUIMR bit 4Master Abort - bit 13 PCI Master Abort - bit 3 PATUIMR bit 5Detected Parity Error - bit 15 Detected Parity Error - bit 9 PATUIMR bit 7Master Parity Error - bit 8 PCI Master Parity Error - bit 0 PATUIMR bit 2Target Abort (master) - bit 12 PCI Target Abort (master) - bit 2 PATUIMR bit 4N/A P_SERR# Detected - bit 4 ATUCR bit 9Developer’s Manual 5-51