Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipTables2-1 PCI Interrupt Routing Summary.................................................................................................2-42-2 Interrupt Input Pin Descriptions .................................................................................................2-42-3 FIQ1# Interrupt Sources ............................................................................................................2-52-4 FIQ2 Interrupt Sources ..............................................................................................................2-62-5 IRQ Interrupt Sources................................................................................................................2-72-6 Default Interrupt Routing and Status Values .............................................................................2-92-7 Interrupt Control Registers Addresses.....................................................................................2-102-8 PCI Interrupt Routing Select Register (PIRSR) .......................................................................2-112-9 FIQ1 Interrupt Status Register- FIQ1ISR.................................................................................2-122-10 FIQ2 Interrupt Status Register- FIQ2ISR.................................................................................2-142-11 IRQ Interrupt Status Register- IRQISR....................................................................................2-153-1 Commonly Used Terms.............................................................................................................3-23-2 Flash Interface Signals ..............................................................................................................3-53-3 Address Decoding for Flash Memory Space .............................................................................3-73-4 Flash Wait State Profile Programming ......................................................................................3-93-5 SDRAM Interface Signals ........................................................................................................3-113-6 Supported SDRAM Configurations ..........................................................................................3-133-7 SDRAM Address Register Definitions .....................................................................................3-133-8 Address Decoding for SDRAM Memory Space .......................................................................3-143-9 Programming Values for the SDRAM Boundary Registers (SBRx[7:3])..................................3-143-10 SDRAM Address Translation for 64/128/256 Mbit Devices using SA[12:0].............................3-153-11 SDRAM Address Translation for 256 Mbit Devices.................................................................3-153-12 SDRAM Commands ................................................................................................................3-183-13 Syndrome Decoding ................................................................................................................3-293-14 Overlapping Address Priorities ................................................................................................3-333-15 MCU Error Response ..............................................................................................................3-413-16 Memory Controller Register Table...........................................................................................3-443-17 SDRAM Initialization Register - SDIR......................................................................................3-453-18 SDRAM Control Register - SDCR ...........................................................................................3-463-19 Drive Strength Programmability Options .................................................................................3-473-20 SDRAM Base Register - SDBR ...............................................................................................3-483-21 SDRAM Boundary Register 0 - SBR0 .....................................................................................3-493-22 SDRAM Boundary Registers - SBR1.......................................................................................3-503-23 ECC Control Register - ECCR.................................................................................................3-513-24 ECC Log Registers - ELOG0, ELOG1.....................................................................................3-523-25 ECC Address Registers - ECAR0, ECAR1..............................................................................3-533-26 ECC Test Register - ECTST....................................................................................................3-543-27 Flash Base Register 0 - FEBR0...............................................................................................3-553-28 Flash Base Register 1 - FEBR1...............................................................................................3-563-29 Flash Bank Size Register 0 - FBSR0.......................................................................................3-573-30 Flash Bank Size Register 1 - FBSR1.......................................................................................3-583-31 Flash Wait State Registers - FWSR0, FWSR1........................................................................3-593-32 Memory Controller Interrupt Status Register - MCISR ............................................................3-603-33 Refresh Frequency Register - RFR .........................................................................................3-614-1 PCI Configuration Command Access Formats..........................................................................4-74-2 Bridge Configuration Cycle Handling Summary ........................................................................4-84-3 IDSEL Mapping for Type 1 to Type 0 Conversions .................................................................4-104-4 Public/Private PCI Memory IDSEL Select Configurations .......................................................4-13Developer’s Manualxxi