Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.8.9 M7_D3_ownThis duration event counts the duration for which PCI Master 3 is the master on the secondary PCIbus. The counter increments on every clock cycle during which PCI Master 3 is the bus master.11.3.8.10 M7_D4_ownThis duration event counts the duration for which PCI Master 4 is the master on the secondary PCIbus. The counter increments on every clock cycle during which PCI Master 4 is the bus master.11.3.8.11 M7_D5_ownThis duration event counts the duration for which PCI Master 5 is the master on the secondary PCIbus. The counter increments on every clock cycle during which PCI Master 5 is the bus master.11.3.8.12 M7_PPCI_IOP_ownThis duration event counts the duration for which the Intel ® 80312 I/O companion chip is themaster on the primary PCI bus. The counter increments on every clock cycle during which theIntel ® 80312 I/O companion chip is the bus master.11.3.8.13 M7_PPCIbus_idleThis duration event increments the counter ever y primary PCI bus idle cycle. An idle cycle occurswhen there is no activity on the bus due to data being transferred and/or the bus is not in anoverhead cycle. An overhead cycle is a cycle when a master owns the bus, however the master isunable to send data or the target is unable to receive data - hence no data is transferred.11.3.8.14 M7_PPCIbus_busyThis duration event increments counter every PCI data cycle. Data cycles comprise two instances:• The Intel ® 80312 I/O companion chip as a master on the bus is involved in data transfers toother masters.• External masters initiate data transfers to either the Intel ® 80312 I/O companion chip or toother masters on the bus.11.4 InterruptsThe Programmable Event Counters and the Global Time Stamp Counter generate interrupts to theIntel ® 80312 I/O companion chip. When bit 0 (enable/disable bit) in the Global Timer ModeRegister (GTMR) is set, the Global Time Stamp Counter interrupts the Intel ® 80200 processor onan overflow. Any Programmable Event Counter interrupts the processor on an overflow by settingthe corresponding bit in the Event Monitoring Interrupt Status Register (EMISR). Setting a bit inthis register generates an interrupt to the FIQ# interrupt pin of the Intel ® 80200 processor. Whenmultiple counters overflow, each counter that overflows sets the corresponding bit in the EMISR.The FIQ# pin of the Intel ® 80200 processor receives interrupts from multiple sources through theFIQ1 interrupt latch. A valid interrupt from any source sets the bit in the latch and outputs alevel-sensitive interrupt to the Intel ® 80200 processor FIQ# pin.Developer’s Manual 11-21