Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.8.2 I 2 C Status Register- ISRI 2 C interrupts are signalled through FIQ2# and the FIQ2 Interrupt Status Register (FIQ2ISR),which shows the pending FIQ2 interrupts (see Chapter 2, “PCI and Peripheral Interrupt ControllerUnit”). FIQ2# is set by the I 2 C Interrupt Status Register (ISR). Software uses the ISR bits to checkthe status of the I 2 C unit and bus. ISR bits (bits 9-5) are updated after the Ack/Nack bit hascompleted on the I 2 Cbus.The ISR is also used to clear interrupts signalled from the I 2 C Bus Interface Unit. These are:• IDBR Receive Full• IDBR Transmit Empty• Slave Address Detected• Bus Error Detected• STOP Condition Detect• Arbitration LostTable 12-10. I 2 C Status Register - ISR (Sheet 1 of 2)IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc rc rc rc rc ro ro ro roPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address1684HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:11 000000H ReservedBus Error Detected:0 = No error detected.1= TheI 2 C unit sets this bit when it detects one of the following error conditions:10 0 2 • As a master transmitter, no Ack was detected on the interface after a byte was sent.• As a slave receiver, the I 2 C unit generates a Nack pulse.NOTE: When an error occurs, I 2 C bus transactions continue. Software must guarantee that misplacedSTART and STOP conditions do not occur. See Section 12.3.4, “Arbitration” on page 12-12.09 0 20 = No slave address detected.1= I 2 C unit detected a 7-bit address that matches the general call address or ISAR. An interrupt isSlaveAddressDetected:signalled when enabled in the ICR.08 0 2 0 = No general call address received.GeneralCallAddressDetected:1= I 2 C unit received a general call address.12-30 Developer’s Manual