Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.39 Secondary ATU Interrupt Status Register - SATUISRThe Secondary ATU Interrupt Status Register is used to notify the Intel ® 80200 processor of thesource of a Secondary ATU interrupt. In addition, this register is written to clear the source of theinterrupt to the interrupt unit of the Intel ® 80312 I/O companion chip. All bits in this register areRead/Clear.Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the Secondary ATU StatusRegister (these bits are set at the same time by hardware but need to be cleared independently).Bit 7 is set by an error associated with the internal bus of the Intel ® 80312 I/O companion chip.The conditions that result in a Secondary ATU interrupt are cleared by writing a 1 to theappropriate bits in this register.Note that bits 4:0, bit 7, and bit 9 can result in an IRQ# interrupt being driven to the Intel ® 80200processor.Table 5-67. Secondary ATU Interrupt Status Register - SATUISR (Sheet 1 of 2)IOPAttributesrv31rvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rv rc rv rv rc rc rc rc rcPCIAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrororvrorvrvrororororoIntel ® 80200 Processor Local Bus Address1294HPCI Configuration Address Offset94H - 97HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:11 000000H Reserved10 0 2 S_SERR# Asserted - set when S_SERR# is asserted on the PCI bus by the secondary ATU.09 0 2• Read Data Parity Error when the SATU is Master (outbound read). Read Data Parity Errors whenDMA Channel 2 is a master ARE NOT logged here, and instead are logged in the DMA Channel 2Detected Parity Error - set when a parity error is detected on the secondary PCI bus even when theSATUCMD register’s Parity Error Response bit is cleared. Set under the following conditions:• Write Data Parity Error when the SATU is a slave (inbound write).CSR.• Any Address Parity Error on the Secondary Bus (including one generated by the SATU or DMAChannel 2 when loopback is enabled).08 0 2 ReservedInternal Bus Master Abort - set when a transaction initiated by the ATU internal bus master interface07 0 2 ends in a Master-abort.06:05 00 2 Reserved04 0 2 S_SERR# Detected - set when S_SERR# is detected on the PCI bus by the secondary ATU.PCI Master Abort - set when a transaction initiated by the ATU PCI master interface ends in a03 0 2 Master-abort.PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a02 0 2 Target-abort.PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on01 0 2 thePCIbuswithatargetabort.5-102 Developer’s Manual