Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80312 I/O Companion Chip Arbitration7.3 PCI Selector OperationFigure 7-1 shows the block diagram of all the arbitration components in the Intel ® 80312 I/Ocompanion chip.The Intel ® 80312 I/O companion chip arbitration includes one PCI selector block.The responsibility of the PCI selector is to assert an external REQ# on behalf of one of the internalmasters. The PCI selector also routes the external GNT# to the requesting internal agent.The Primary PCI bus has four potential masters from the Intel ® 80312 I/O companion chip:DMA0, DMA1, PATU, and BDG. If one of the Intel ® 80312 I/O companion chip masters needs theprimary PCI bus and asserts its REQ#, the Primary PCI selector (PSEL) asserts P_REQ#. Whenthe Primary PCI slave asserts P_GNT#, the PSEL asserts the GNT# for the master requesting thebus.When a primary master asserts one of the four REQ# signals, the PSEL asserts P_REQ#. Forthecase of multiple requests, the selector must arbitrate between the requesting agents. The arbitrationis a simple round-robin algorithm.7.3.1 Primary PCI Bus Arbitration ParkingWhen the primary PCI bus is parked on the Intel ® 80312 I/O companion chip, the last mastercontinues to assert P_AD[31:0], P_C/BE[3:0]#,andP_PAR. This prevents the PCI bus fromfloating.Note:The 64-bit extension signals (P_AD[63:32], P_C/BE[7:4]#,andP_PAR64) are not actively drivenwhen the secondary PCI bus is parked on the Intel ® 80312 I/O companion chip. Per the PCI LocalBus Specification, Revision 2.2, pull-ups provided on the motherboard ensure that these signals arestable.7.4 Master Latency Timer OperationEach PCI device must contain a Master Latency Timer (MLT). This timer defines the minimumtime a PCI master may own the PCI bus. If no other agent is requesting the bus once the MLTexpires, the master may continue to use the bus. Once another agent requests the PCI bus and thecurrent bus master’s latency timer has expired, the current master must release the bus as soon aspossible to allow the requesting agent bus ownership.7.4.1 Primary and Secondary PCI Master Latency TimersEach PCI interface of the Intel ® 80312 I/O companion chip (primary and secondary) contains amaster latency timer (MLT) for use by the internal resources when they are acting as PCI busmasters. Both ATUs, the DMA channels, and the bridge interfaces use an MLT. MLT usage isexplained in the PCI Local Bus Specification, Revision2.2.As defined by the PCI specification, a PCI bus master must release bus ownership as soon as possiblewhen it has lost its GNT# and the MLT has expired. After the MLT expires, the bus master mustrelinquish the bus when an external device or one of the internal resources requests the bus.7-10 Developer’s Manual