Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unitbuses don’t maintain the same PCI bandwidths, the bridge PMW Queues maintain data integrityand guarantee no data is lost by disconnecting a filling master on an initiating bus before anoverflow condition exists.The PMW Queues are capable of streaming write data from an initiating bus to a target busassuming no prior PMW transactions exist in the PMW Queue (by the time the queue fills) beingaccessed and the target interface is capable of acquiring the bus and the addressed target device.This can continue until the target initiates termination (Disconnect or Target-Abort), the bridgeinitiates termination on the target bus (Time-out), the PMW Queue fills, the transaction is an MWIand a full cacheline is not free in the PMW Queue, or the initiator completes the required numberof write transfers. In the situation where the target bus transaction terminates while the initiator isstill transferring data, the PMW Queue will fill and a Disconnect would occur in the same situationas when the initiator started the original transaction (see previous paragraph). In addition, neitherthe Primary or Secondary interface of the bridge will insert target wait states (deassertion ofTRDY#) or master wait states (deassertion of IRDY#) to support the sustaining of a streamingtransaction through the bridge. The target interface of the bridge may insert master wait states toguarantee the transfer of an entire cacheline during Memory Write and Invalidate transfers. SeeSection 4.6.6.4, “Memory Write and Invalidate Command” on page 4-45.The bridge unit is capable of supporting simultaneous write posting in both directions across thebridge.When a memory write transaction is accepted on the initiating bus interface, and transactionordering supports the immediate draining of the current transaction (see Section 4.7.2), the defaultis for the target bridge interface to assert REQ# once the first PCI dataphase has been entered intothe posted write queue. In this case, the PCI dataphase is a 32-bit word when the master is driving32-bits or a 64-bit word when the master is driving 64-bits.The bridge only supports the linear incrementing burst mode for Memory write commands. Thebridge will signal a Disconnect to the initiator after the transfer of the first data phase when theburst mode is not linear incrementing.See Section 4.7.1.1 for complete details on posted memory write queues.4.6.6.3 Memory Write CommandA PCI initiator will use the memory write command for transferring data to one of the memoryaddress spaces defined in one or both of the MBR/MLR and the PMBR/PMLR register pairs.Memory write transactions can be either posted or delayed transactions. This is determined by thePosting Disable bit in the Extended Bridge Control Register. When clear, posted transactions areused. When set, delayed transactions are used.Delayed Memory Write commands will only transfer one 32-bit PCI data phase. This meansFRAME# will only be asserted for one clock on the target interface and that the initiating interfacewill signal a target Disconnect after the first data transfer. Refer to the PCI Local Bus Specification,Revision 2.2 for more details.4-44 Developer’s Manual