Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.11.1 Accelerator Control Register - ACRThe Accelerator Control Register (ACR) specifies parameters that dictate the overall operatingenvironment. The ACR should be initialized prior to all other AAU registers following a systemreset. Table 10-4 shows the register format. This register can be read or written while the AAU isactive.Table 10-4.Accelerator Control Register - ACRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rwPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 processor local bus address1800HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:03 0 Reserved02 0 2512 Byte Buffer Enable - when set, causes the AAU to use only 512 bytes of the 1KB data buffer whileprocessing all descriptors.NOTES: The 1KB data buffer consumes 128 data cycles on the Internal bus every time the AAU isgranted the Internal Bus (assuming BC remains > 1K). Depending on the application, overallperformance may be improved by throttling down the IB usage to 64 data cycles per Internal Bus grant.01 0 • The AAU completes a transfer and the Accelerator Next Descriptor Address Register is non-zero. InChain Resume - when set, causes the AAU to resume chaining by re-reading the current descriptorlocated at the address in the Accelerator Descriptor Address Register when the AAU is idle (AAU Activebit in the ASR is clear) or when the AAU completes a transfer. This bit is cleared by hardware wheneither:2this case, the AAU proceeds to the next descriptor in the chain.• The AAU re-reads the chain descriptor located at the address in the Accelerator Descriptor AddressRegister and loads the Next Descriptor Address of that descriptor into the Accelerator NextDescriptor Address Register00 0 2AAU Enable - When set, the AAU enables transfers. When clear, the AAU disables any transfer.Clearing this bit when the AAU is active suspends the current transfer at the earliest opportunity byhalting all internal bus transactions. The AAU does not initiate any new transfers when this bit is cleared.Data held in queues remains valid. Setting the bit after the AAU is suspended causes the AAU toresume the previously ongoing transfer.10-24 Developer’s Manual
Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.11.2 Accelerator Status Register - ASRThe Accelerator Status Register (ASR) contains status flags that indicate status. This register istypically read by software to examine the source of an interrupt. See Section 10.9 for a descriptionof the error conditions that are reported in the ASR. See Section 10.8 for a description of interruptscaused by the Application Accelerator.When an AAU error occurs, application software should check the status of Accelerator Activeflag before processing the interrupt.Table 10-5.Accelerator Status Register - ASRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro rc rc rv rc rc rv rv rv rv rvPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 processor local bus address1804HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:11 000000H Reserved10 0 2• byte count reached zero and last chain descriptor is encountered (NULL value detected for NextDescriptor Address in chain descriptor)Accelerator Active Flag - indicates the AAU is either active (in use) or idle (available). When set,indicates the AAU is in use and actively performing an operation. When clear, indicates the channel isidle and available to be configured for a new operation. The AAU clears the Accelerator Active flag whenthe previously configured transfer completes as a result of:• Internal Bus Errors• Last chain descriptor is processed (NULL value detected for Next Descriptor Address in chaindescriptor) and ADCR.dwe = 0.The Accelerator Active flag is set once a Chain Descriptor is read from memory.End of Transfer Interrupt Flag - set when the AAU has signalled an interrupt to the Intel09 0 ® 802002 processor after processing a descriptor but it is not the last descriptor in a chain.End of Chain Interrupt Flag - set when the channel has signalled an interrupt to the Intel08 0 ® 802002 processor after processing a descriptor that is the last in a chain.07:06 0 2 ReservedThis bit is set when a Master-abort occurs during a transaction when the AAU is the master on the05 0 2 internal bus.04:00 0 2 ReservedDeveloper’s Manual 10-25
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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DMA Controller Unit 9This chapter d
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Intel 80312 I/O Companion Chip - ECEE

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