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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>PCI Address Translation UnitIn Example 5-1 on page 5-37, the inbound write and outbound read queues of an ATU are shown.In this example, transaction A entered the write queue at Time 0. Next, the ATU entered read datainto the outbound read queue at Time 1 (Transaction B). Finally, before the previous transactionscould be cleared, another inbound write, Transaction C, was entered into the IWQ. The ordering inTable 5-7 states that nothing can pass an inbound write and therefore Transaction A must completeon the internal bus before Transaction B since an outbound read completion can not pass aninbound write. Also, Transaction A must complete before Transaction C since an inbound write cannot pass another inbound write. Once Transaction A completes, Transaction C moves to the head ofthe IWQ. The two transactions at the head of the queues moving data in an inbound direction arenow Transaction C, an inbound write, and Transaction B, an outbound read completion. Orderingstates that an inbound write may pass an outbound read completion. This means that the prioritymechanism now takes over to decide which completes (defined in the next section). In this case,when the CIU acquires the internal bus first, Transaction B completes. If the ATU acquires theinternal bus first, Transaction C completes. Note that ordering enforced the completion ofTransaction A but priority dictated the completion of Transactions B and C.The first action performed to determine which transaction is allowed to proceed (either inbound oroutbound) is to apply the rules of ordering as defined in Table 5-7 and Table 5-8. Any box markedNo must be satisfied first. For example, when an inbound read request is in P_ITQ1 and it waslatched after the data in the P_IDWQ arrived (this is a configuration write), then ordering statesthat an Inbound Read Request may not pass an Inbound Configuration Write Request. Therefore,the Inbound Configuration Write Request must be cleared out of P_IDWQ before the InboundRead Request is attempted on the internal bus. Once transaction ordering is satisfied, the boxesmarked Yes are now resolved.5-38 Developer’s Manual

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