Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator UnitThe XOR algorithm and methodology followed once a chain descriptor has been configured isdetailed below:1. The Application Accelerator as a master on the bus initiates data transfer from the addresspointed at by the First Source Address Register (SAR1). As this is the first transfer in thecurrent chain descriptor, the data is transferred directly to the store queue. The number of bytestransferred to the store queue is 1K (or 512 Bytes when the 512 Byte Buffer Enable Bit in theACR register is set). The total number of bytes to XOR-transfer is specified by the Byte Count(BC)fieldinthechaindescriptor.Note:Note:The Application Accelerator operates on a buffer of 1K or 512 bytes of data at a time depending onthe value of the 512 Byte Buffer Enable bit. When the Byte Count Register contains a value greaterthan the buffer size, the AAU completes the XOR-transfer operation on the first buffer of dataobtained from each Source Register (SAR1 - SAR4), then proceeds with the next buffer of data.This process is repeated until the BCR contains a zero value.2. The Application Accelerator transfers the first eight bytes of data from the address pointed atby the Second Source Address Register (SAR2).3. The boolean unit performs the bit-wise XOR algorithm on the input operands. The inputoperands are the first eight bytes of data read from SAR1 (bytes 1-8) which are stored in thequeue and the first eight bytes of data just read from SAR2 (bytes 1-8).4. The XOR-ed result is transferred to the store queue and stored in the first eight bytes(bytes 1-8) overwriting previously stored data.5. The Application Accelerator transfers the next eight bytes of data (bytes 9-16) from addresspointed at by the Second Source Address Register (SAR2).6. The boolean unit performs the bit-wise XOR algorithm on the input operands. The inputoperands are the next eight bytes of data read from SAR1 (bytes 9-16 stored in the queue) andthe eight bytes of data read from SAR2 in Step-5.7. Step-5 and Step-6 (Data transfer & XOR) are repeated until all data pointed at by SAR1 isXOR-ed with the corresponding data pointed at by SAR2. The store queue now contains abuffer full of XOR-ed data, the source addresses for which were specified in SAR1 and SAR2.8. Steps 1-7 are repeated once again. The first input to the XOR unit is the data held in the storequeue and the second input is the data pointed at by SAR3.9. The above steps are repeated once more. The first input to the XOR unit is the data held in thestore queue and the second input is the data pointed at by SAR4.10. Once Steps 1-9 are completed, the XOR operation is complete for the first full buffer of thecurrent chain descriptor. When the Destination Write Enable Bit in the Accelerator DescriptorControl Register (ADCR) is set, the data in the store queue is written to local memory at theaddress pointed to by the Destination Address Register (DAR). When the Destination WriteEnable Bit in the ADCR is not set, the data is not written to local memory and is held in thequeue. Steps 1-9 are repeated until all the bytes of data have undergone the XOR-transferoperation.When the ABCR register contains a value greater than the buffer size and the ADCR.dwe bit iscleared, the AAU only reads the first buffer of data and perform the specified function. It does notread the remaining bytes specified in the ABCR. Further, the AAU proceeds to process the nextchain descriptor when it is specified.10-12 Developer’s Manual