Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.8.5 Inbound Interrupt Mask Register - IIMRThe Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel ® 80200 processorinterrupts generated by the Messaging Unit. Each bit in the Mask register corresponds to aninterrupt bit in the Inbound Interrupt Status Register.Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. Theyonly affect the generation of the Intel ® 80200 processor interrupt.Table 6-11.Inbound Interrupt Mask Register - IIMR3128 24 20 16 12 8 4 0PCI IOPAttributes Attributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrw rw rwrw rw rwrw rw rw rwrw rw rw rwIIMRIntel ® 80200 Processor Local Bus Address1328HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:07 000000H 0 2 Reserved06 0 2Index Register Interrupt Mask - When set, this bit masks the interrupt generated bythe MU hardware when an Index Register has been written after a PCI transaction.05 0 2Outbound Free Queue Full Interrupt Mask - When set, this bit masks the IRQ interruptgenerated when the Outbound Free Head Pointer becomes equal to the Tail Pointerand the queue is full.Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated04 0 2 by the MU hardware when the Inbound Post Queue has been written.IRQ Doorbell Interrupt Mask - When set, this bit masks the IRQ Interrupt when the03 0 2 IRQ Interrupt bit of the Inbound Doorbell Register is set.Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated02 0 2 when at least one FIQ2 Interrupt bit in the Inbound Doorbell Register is set.Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 101 0 2 Interrupt generated by a write to the Inbound Message 1 Register.Inbound Message 0 Interrupt Mask - When set, this bit masks the Inbound Message 000 0 2 Interrupt generated by a write to the Inbound Message 0 Register.6-22 Developer’s Manual