Intel 80312 I/O Companion Chip - ECEE

.Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.20 Primary Inbound ATU Limit Register - PIALRPrimary inbound address translation occurs for data transfers occurring from the PCI bus(originated from the primary PCI bus) to the Intel ® 80312 I/O companion chip internal bus. Theaddress translation block converts PCI addresses to internal bus addresses.The primary inbound translation base address is specified in Section 5.7.10. When determiningblock size requirements — as described in Section 5.7.15 — the primary translation limit registerprovides the block size requirements for the primary base address register. The remaining registersused for performing address translation are discussed in Section 5.2.1.1.The Intel ® 80312 I/O companion chip value register’s programmed value must be naturally alignedwith the base address register’s programmed value. The limit register is used as a mask; thus, thelower address bits programmed into the Intel ® 80312 I/O companion chip value register areinvalid. Refer to the PCI Local Bus Specification, Revision 2.2 for additional information onprogramming base address registers.Table 5-48.Bits 31 to 12 within the PIALR have a direct effect on the PIABAR register, bits 31 to 12, with aone to one correspondence. A value of 0 in a bit within the PIALR makes the corresponding bitwithin the PIABAR a read only bit which always returns 0. A value of 1 in a bit within the PIALRmakes the corresponding bit within the PIABAR read/write from PCI. Note that a consequence ofthis programming scheme is that unless a valid value exists within the PIALR, all writes to thePIABAR has no effect since a value of all zeros within the PIALR makes the PIABAR a read onlyregister.Primary Inbound ATU Limit Register - PIALRIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rw rw rw rw rwrw rw rw rw rw rw rw rwrvrvrvrvrvrvrvrvrvrvrvrvIntel ® 80200 Processor Local Bus Address1240HPCI Configuration Address Offset40H - 43HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 FF000HPrimary Inbound Translation Limit - This readback value determines the memory block size required forthe primary ATU translation unit. This defaults to an inbound window of 16MB.11:00 000H ReservedDeveloper’s Manual 5-81