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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>I 2 C Bus Interface Unit12.3.2 Data and Addressing ManagementData and slave addressing is managed via the I 2 C Data Buffer Register (IDBR) and the I 2 CSlaveAddress Register (ISAR). The IDBR (see Section 12.8.4, “I 2 C Data Buffer Register- IDBR” onpage 12-33) contains data or a slave address and R/W# bit. The ISAR contains the <strong>Intel</strong> ® <strong>80312</strong>I/O companion chip’s programmable slave address. Data coming into the I 2 C unit is received intothe IDBR after a full byte is received and acknowledged. To transmit data, the processor writes tothe IDBR, and the I 2 C unit passes this onto the serial bus when the Transfer Byte bit in the ICR isset. See Section 12.8.1, “I 2 C Control Register- ICR” on page 12-27.When the I 2 C unit is in transmit mode (master or slave):1. Software writes data to the IDBR over the internal bus. This initiates a master transaction orsends the next data byte, after the IDBR Transmit Empty bit is sent.2. The I 2 C unit transmits the data from the IDBR when the Transmit Empty bit in the ICR is set.3. When enabled, an IDBR Transmit Empty interrupt is signalled when a byte is transferred onthe I 2 C bus and the acknowledge cycle is complete.4. When the I 2 C bus is ready to transfer the next byte before the processor has written the IDBR(and a STOP condition is not in place), the I 2 C unit inserts wait states until the processorwrites a new value into the IDBR and sets the ICR Transfer Byte bit.When the I 2 C unit is in receive mode (master or slave):1. The processor reads the IDBR data over the internal bus after the IDBR Receive Full interruptis signalled.2. The I 2 C unit transfers data from the shift register to the IDBR after the Ack cycle completes.3. The I 2 C unit inserts wait states until the IDBR is read. Refer to Section 12.3.3, “I 2 CAcknowledge” on page 12-11 for acknowledge pulse information in receiver mode.4. After the processor reads the IDBR, the I 2 C unit writes the ICR’s Ack/Nack Control bit andthe Transfer Byte bit, allowing the next byte transfer to proceed.Developer’s Manual 12-9

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