Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80312 I/O Companion Chip Arbitration7.6.4 Multi-Transaction Timer Register - MTTRThe Multi-Transaction Timer Register defines the duration, which the Intel ® 80200 processor canaccess, through the CIU, retains GNT[8]# across back-to-back transactions. This is an 8-bit valueallowing up to 255 dedicated internal bus cycles for as long as REQ[8]# is asserted. A value of zeroeffectively disables the MTT. This register is part of the local arbitration configuration register space andis accessible from the Intel ® 80200 processor.Table 7-11.Multi-Transaction Timer Register - MTTRPCI IOPAttributes Attributes31 28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rwna na na na na na na na na na na na na na na rw na na na na na na na na na na na na na na na naIntel ® 80200 Processor Local Bus Address Attribute Legend:1608HRV = ReservedPR = PreservedRS = Read/SetBit Default DescriptionRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not Accessible31:8 000000H Reserved7:0 00HMulti-Transaction Timer Preload Value - Indicates the minimum number of clocks amaster is allowed to hold the PCI bus for a single transaction.7-16 Developer’s Manual