Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.9 Register DefinitionsThere is one peripheral memory-mapped registers (PMMR) for the CIU.8.9.1 CIU Interrupt Status Register - CIUISRThe CIU Interrupt Status Register (CIUISR) records the assertion of interrupts to the Intel ® 80200processor.IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rv rvPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Processor Local Bus Address1644HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearBit Default Description31:03 00000000H Reserved02 0 2has signalled an IRQ# interrupt to the Intel ® 80200 processor. This bit is cleared by software.Note that a Master-Abort received from the ATU is not recorded as an internal bus Master-Abort inInternal Bus Master-Abort - When set, the CIU has detected a Master-Abort on the Internal Bus andthis bit.01:00 0 2 Reserved8-14 Developer’s Manual