Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.4 Configuration AccessesThis section describes how the bridge handles PCI configuration read and write commands.There are two classes of targets for PCI configuration commands:• devices that reside on the Primary PCI bus• devices that reside on hierarchical (Secondary) PCI buses that are accessed via PCI-to-PCIbridge chipsThe encoding of the address during a configuration command distinguishes the target of thecommand. Figure 4-3 and Table 4-1 show the different address encodings associated with each PCIconfiguration command type. Type 0 and Type 1 commands are distinguished by address bitsAD[1:0].Table 4-1.PCI Configuration Command Access FormatsBit FunctionType 0 CommandsBit Position (# of Bits)Type 1 CommandsBit Position (# of Bits)Command Type 1:0 (2) 1:0 (2)Register Number 7:2 (6) 7:2 (6)Function Number 10:8 (3) 10:8 (3)Device Number N/A 15:11 (5)Bus Number N/A 23:16 (8)Reserved 31:11 (20) 31:24 (8)Figure 4-3.PCI Configuration Access Formats31 11 10 8 7 2 1 0ReservedFunctionNumberRegisterNumber00Type 031 24 23 16 15 11 10 8 7 2 1 0ReservedBusNumberDeviceNumberFunctionNumberRegisterNumber01Type 1A Type 0 configuration command on the Primary interface may be accepted or ignored by thebridge depending on the value of the P_IDSEL input. A Type 1 configuration command on thePrimary interface may be ignored, forwarded downstream unaltered, converted to a Type 0command on the Secondary interface, or converted to a Special Cycle on the Secondary interface.Developer’s Manual 4-7