Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitFor I/O transactions, the internal bus address is bitwise ANDed with the inverse of 64 Kbyteswhich clears the upper 16 bits of address. Address aliasing can be prevented by programming theoutbound window value registers on boundaries equivalent to the window’s length, but this is onlyenforced through application programming. PCI I/O addresses are byte addresses and not wordaddresses. The PCI I/O address’s two least significant bits are determined by byte enables that theprocessor issues. For example, when the Intel ® 80200 processor performs a 2-byte write andgenerates byte enables of 0011 2 , the ATU sets the two least significant bits of PCI I/O address to10 2 .Note:Figure 5-6.When the Intel ® 80200 processor data cache is enabled for accesses to the Outbound I/O Window,the byte enables generated by the Intel ® 80200 processor are always 00 2 for Byte and Shortaccesses.Outbound Address Translation Windows64 Mbytes64 Kbytes8000 0000HPrimary Memory Window83FF FFFFH8400 0000HPrimary DAC Window87FF FFFFH8800 0000HSecondary Memory Window8BFF FFFFH8C00 0000HSecondary DAC Window8FFF FFFFH9000 0000HPrimary I/O Window9000 FFFFH9001 0000HSecondary I/O Window9001 FFFFH8000 0000HATU OutboundMemory and DAC CycleTranslation Windows8FFF FFFFH9000 0000HATU OutboundI/O CycleTranslation Windows9001 FFFFH5-18 Developer’s Manual