Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitDuring a downstream Write Completion Cycle on the target bus when the bridge is trying to deliverenqueued write data, the Secondary bridge interface has the following actions with the givenconstraints when S_PERR# is detected during the transaction:• The Data Parity Error Detected bit is set in the Secondary Status Register (SSR) when theSecondary Parity Error Response Bit is set in the BCR. When the Data Parity Error Detectedbit in the SSR is set and the Secondary PCI Master Parity Error Interrupt Mask in the SDER isclear, set the PCI Master Parity Error bit in the SBISR.• The Secondary interface of the bridge captures the error completion status for delivery back tothe initiator on the Primary interface.During a upstream Write Completion Cycle on the target bus when the bridge is trying to deliverenqueued write data, the Primary bridge interface has the following actions with the givenconstraints when P_PERR# is detected during the transaction:• The Data Parity Error Detected bit is set in the Primary Status Register (PSR) when thePrimary Parity Error Response Bit is set in the PCR. When the Data Parity Error Detected bitin the PSR is set and the Primary PCI Master Parity Error Interrupt Mask in the SDER is clear,set the PCI Master Parity Error bit in the PBISR.• The Primary interface of the bridge captures the error completion status for delivery back tothe initiator on the Secondary interface.For the original write transaction to be completed, the initiator will retry the transaction on theinitiating bus and the bridge will return the status from the target bus, completing the transaction. Adata parity error can occur in this scenario on the initiating bus that was not detected during thewrite completion cycle on the target bus or a parity error can occur in response to a parity error thatdid occur during the write completion cycle on the target bus (contained with the status returned bythe bridge).For downstream delayed completion transaction on the initiating bus where a data parity erroroccurs that did not occur on the target bus (i.e. status being returned is normal completion) thePrimary bridge interface performs the following actions with the given constraints:• When the Primary Parity Error Response Bit is set in the PCR, the Primary interface claims thetransaction by asserting P_TRDY# and two clocks later asserts P_PERR#. TheDelayedCompletion cycle in the DWC Queue remains since the data of retried command did not matchthe data within the queue.When the Primary Parity Error Response Bit is clear in the PCR, the Primary interfacewill retry the transaction with no other response. A new transaction is not enqueued due toqueue architecture constraints (see Section 4.7.1).• The Detected Parity Error bit is set in the Primary Status Register (PSR) in the followingscenario only: a transaction with bad parity was forwarded to the Secondary bus, which meansthat the Parity Response Enable Bit (PCR) associated with the Primary bus is not set. Whenthe Primary Detected Parity Error Interrupt Mask bit is clear in the SDER, set the DetectedParity Error bit in the PBISR.Note that when the parity of the original request does not match the parity of thetransaction the Primary master sends for a completion, the bridge will not detect a matchfor the completion attempt and will retry the transaction. In this case the transaction willmost likely never be completed, and the enqueued data will eventually be discarded.4-70 Developer’s Manual