Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.7.1.2 Upstream/Downstream Delayed Read Completion QueuesThe Delayed Read Completion Queues (DRC) in the bridge hold the read data obtained during aread completion cycle on the target bus of a Delayed Read Request transaction. The bridge unit hasthree DRC Queues for each direction of data through the bridge unit. These DRC Queues aredifferent sizes allowing for larger read prefetch sizes when Memory Read Line and Memory ReadMultiple commands are used. I/O Reads and Configuration Reads are constrained to the 4-bytequeues on each side of the bridge (see Table 4-14).Only the data from a delayed read completion cycle is stored in the DRC queue. The addresslatched from the delayed read request cycle on the initiating bus is stored in the dedicatedtransaction queues. U_DRC0 through U_DRC2 use U_TRQ0 through U_TRQ2 respectively andD_DRC0 through D_DRC2 use D_TRQ0 through D_TRQ2 respectively.Transaction queues U_TRQ0, U_TRQ1, and U_TRQ2 have an additional 32-bits of address spacefor holding the upper 32-bits of an upstream DAC read transaction. Upstream DACs areconstrained to U_DRC0, U_DRC1, and U_DRC2.To maximize read throughput, the larger DRC queues are assigned to the memory read hintcommands to maximize the amount of data read on the target bus interface. I/O Reads,Configuration Reads, and non-prefetchable Memory Reads are assigned to the dedicated 4-bytequeues. The assignment schemes are in Table 4-15 for the downstream read queues and Table 4-16for the upstream read queues. Refer to Table 4-12 for downstream read prefetch data sizes andTable 4-13 for upstream read prefetch sizes.Table 4-15.Table 4-16.D_DRC AssignmentsPCI CommandQueue AssignmentPrefetchNon-PrefetchMemory Read Multiple 64 Byte Queue 4 Byte QueueMemory Read Line 64 Byte Queue 4 Byte QueueMemory Read 64 Byte Queue 4 Byte QueueI/O Read N/A 4 Byte QueueConfiguration Read N/A 4 Byte QueueU_DRC AssignmentsPCI CommandQueue AssignmentPrefetchNon-PrefetchMemory Read Multiple 128 Byte Queue 4 Byte QueueMemory Read Line 128 Byte Queue 4 Byte QueueMemory Read 128 Byte Queue 4 Byte QueueI/O Read N/A 4 Byte QueueThe exact amount of data read by the master state machine on the target interface depends upon thesize of the queue assigned to the request cycle, read command used, prefetchable ornon-prefetchable, and how much data the PCI target device delivers. Table 4-12 and Table 4-13show the amounts of data attempted to be read for the different memory read commands inprefetchable and non-prefetchable address spaces. When an entry in Table 4-12 and Table 4-13states a prefetch size of 128 bytes and the target PCI device on the target bus disconnects the bridgemaster interface before reaching the prefetch size, the DRC is complete on the target bus and isallowed to be returned to the initiator. Additional cycles are not initiated to fill the DRC queue tothe predefined prefetch data size. PCI error conditions override all prefetch amounts (i.e., amaster-abort and target-abort conditions).4-50 Developer’s Manual