Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitExample 4-1. Downstream Data Path Queue CompletionUpstream Delayed Read Completion Queue 0B B B B B B B BCCCCCCCAAAAAAAADownstream Posted Memory Write QueueUpstream Delayed Read Completion Queue 0B B B B B B B BCCCCCCCCDownstream Posted Memory Write QueueIn Example 4-1., the downstream write data queue (D_PMWD) and an upstream read completionqueue (U_DRC0) of the bridge are shown. In this example, transaction A entered the write queue atTime 0. Next, the bridge entered read completion data into the upstream read queue at Time 1(Transaction B). Finally, before the previous transactions could be cleared, another downstreamwrite, Transaction C, was entered into the downstream write data queue. The ordering inTable 4-17 states that nothing can pass a PMW and therefore Transaction A must complete on theSecondary bus before Transaction B is allowed to complete since an upstream read completion cannot pass a downstream posted memory write. Also, Transaction A must complete beforeTransaction C since a PMW can not pass another PMW. Once Transaction A completes,Transaction C moves to the head of the downstream posted memory write queue. The twotransactions at the head of the queues moving data in downstream direction are now Transaction C,a downstream posted memory write, and Transaction B, an upstream read completion. Orderingstates that a PMW may pass a read completion. This means that the priority mechanism now takesover to decide which will complete since a YES condition from Table 4-17 is now present. In thiscase, when the PCI master on the Secondary bus acquires the Secondary bus first, Transaction Bwill complete. When the Secondary interface of the bridge acquires the Secondary bus first,Transaction C will complete. Note that ordering enforced the completion of Transaction A butpriority dictated the completion of Transactions B and C.The first action performed to determine which transaction is allowed to proceed (either upstream ordownstream) is to apply the rules of ordering as defined in Table 4-17. Any box marked No mustbe satisfied first. For example when a downstream read request is in the D_TRQx queue and it waslatched after the data in the D_PMW arrived, then ordering states that a Read Request may not passa Posted Memory Write; therefore the Posted Memory Write must be cleared out of the D_PMWbefore the Read Request is attempted on the Secondary bus. Once transaction ordering is satisfied,the boxes marked Yes are now resolved based on the priority mechanism in Section 4.7.2.Developer’s Manual 4-53