Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.3.2 SDRAM AddressingSDRAM addressing for 64/128/256 Mbit Devices using SA[12:0]Table 3-10 illustrates how the internal address is mapped to the SA[12:0] lines for 64/128/256 MbitSDRAM devices.Table 3-10.SDRAM Address Translation for 64/128/256 Mbit Devices using SA[12:0]SA[12:0] 12 11 10 9 8 7 6 5 4 3 2 1 0Row I_AD[25] I_AD[22] I_AD[21] I_AD[20] I_AD[19] I_AD[18] I_AD[17] I_AD[16] I_AD[15] I_AD[14] I_AD[13] I_AD[12] I_AD[11]Col - - V 1 I_AD[24] I_AD[23] I_AD[10] I_AD[9] I_AD[8] I_AD[7] I_AD[6] I_AD[5] I_AD[4] I_AD[3]NOTES:1. SA[10] is used for precharge variations on the read or write command. See Table 3-12 for more details.2. For the Leaf Selects, see Table 3-6.SDRAM addressing for 256 Mbit Devices using SA[13,11:0]The SA[13] signal can provide the appropriate address signal (I_AD[24]) for 256Mb x 16 SDRAMdevices. Table 3-11 illustrates how the internal address is mapped to the SA[13,11:0] lines. Insteadof connecting SA[12] to the 256Mb x 16 SDRAM, replace it with SA[13]. With this configurationthe 13 rows and 9 columns now provide the correct addressing to the 256Mb x 16 SDRAM.Table 3-11.SDRAM Address Translation for 256 Mbit DevicesSA[13,11:0] 13 11 10 9 8 7 6 5 4 3 2 1 0Row I_AD[24] I_AD[22] I_AD[21] I_AD[20] I_AD[19] I_AD[18] I_AD[17] I_AD[16] I_AD[15] I_AD[14] I_AD[13] I_AD[12] I_AD[11]Col - - V 1 I_AD[23] I_AD[10] I_AD[9] I_AD[8] I_AD[7] I_AD[6] I_AD[5] I_AD[4] I_AD[3]NOTES:1. SA[10] is used for precharge variations on the read or write command. See Table 3-12 for more details.2. For the Leaf Selects, see Table 3-6.Since the MCU supports SDRAM bursting, the MCU increments the column address by four foreach SDRAM read or write burst.The MCU supports a sequential burst type (Figure 3-9). Sequential bursting means that the addressissued to the SDRAM is incremented by the SDRAM device in a linear fashion during the burstcycle.Developer’s Manual 3-15