Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitThe data flow for an inbound read transaction on the internal bus is summarized in the followingstatements:• The ATU internal bus master interface requests the internal bus when a PCI address appears inan ITQ and transaction ordering has been satisfied.• Once the internal bus is granted, the internal bus master interface drives the translated addressonto the bus and wait for a device to claim the transaction. If a Retry is signaled, the request isrepeated. If a master abort occurs, the transaction is considered complete and a master abort isloaded into the associated IRQ for return to the PCI initiator (transaction is flushed once thePCI master has been delivered the master abort).• Once the translated address is on the bus and the transaction has been accepted, the internalbus slave starts returning data. Read data is continuously received by the IRQ until one of thefollowing is true:— The predetermined prefetch data amount is received. This is detailed in Section 5.5.1.2.The ATU internal bus master interface performs a master completion in this case.— A Target Abort is received on the internal bus from the internal bus slave. In this case, thetransaction is aborted. If a Target Abort occurs before 64 bits are ready, notify the PCIside; otherwise, discard the Target Aborted Q-word and take no further action.— The IRQ becomes full. In this case, the ATU master performs a master completion.— The ATU loses ownership of the internal bus and the master latency timer has expired. Amaster completion is performed on the internal bus. If less than 64-bits of data has beenfetched, the ATU IB master interface attempts to reacquire the bus. If not, the bus returnsto idle.— A disconnect with data is received from the internal bus slave. If less than 64-bits of datahas been fetched, the ATU internal bus master interface attempts to reacquire the bus. Ifnot, the bus returns to idle.If the prefetch amount of data has been read and the PCI bus is actively draining the dataon the PCI interface, the ATU continues to read data and latch it into the IRQ to supportinbound read streaming. If the IRQ fills and the PCI interface is active, IB master waitstates are not inserted to support streaming.• Since all inbound reads are promoted to 64-bit internal bus transactions, a disconnect from theinternal bus target with less than 8 bytes returned to the IRQ creates a problem for 64-bit PCIrequestors. To guarantee a minimum of 64-bits of data prefetched for the PCI initiator, theATU reacquires the internal bus.To support PCI Local Bus Specification, Revision 2.2 devices, the ATUs can be programmed toignore the memory read command (Memory Read, Memory Read Line, and Memory ReadMultiple) when trying to match the current inbound read transaction with data in a DRC queuewhich was read previously (DRC on target bus). If the Read Command Alias Bit in the ATUCRregister is set, the ATUs does not distinguish the read commands on transactions. For example, theATU enqueues a DRR with a Memory Read Multiple command and performs the read on theinternal bus. Some time later, a PCI master attempts a Memory Read with the same address as theprevious Memory Read Multiple. If the Read Command Bit is set, the ATU would return the readdata from the DRC queue and consider the Delayed Read transaction complete. If the ReadCommand bit in the ATUCR was clear, the ATU would not return data since the PCI readcommands did not match, only the address.5-12 Developer’s Manual