Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipTest Features14.1.2 TAP PinsThe Intel ® 80312 I/O companion chip TAP pins form a serial port composed of four inputconnections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins aredescribed in Table 14-1. The TAP pins provide access to the instruction register and the test dataregisters.Table 14-1.TAP Controller Pin DefinitionsPin Type DefinitionTCKTMSTDITDOTRST#InputInputInputOutputInputTest Clock provides the clock for the JTAG logic. The JTAG test logic retains its stateindefinitely when TCK is stopped at “0” or “1”.Test Mode is decoded by the TAP controller state machine to control test operations. TMS issampled by the test logic on the rising edge of TCK. TMS is pulled high internally when not driven.Test Data Input is the serial port where test instructions and data is received by the testlogic. Signals presented at TDI are sampled into the test logic on the rising edge of TCK.TDI is pulled high internally when not driven. Data shifted into TDI is not inverted on its wayto the TDO input.Test Data Output is the serial output for test instructions and data from the JTAG test logic.Changes in the state of TDO occur only on the falling edge of TCK. The TDO output isactive only during data shifting (SHDR or SHIR); it is inactive (high-Z) at all other times.Test Reset provides for an asynchronous initialization of the TAP controller. Asserting a logic“0” on this pin puts the TAP controller state machine and all other test logic on the processor inthe Test-Logic-Reset (initial) state. TRST# is pulled high internally when not driven.Note: The system must ensure that TRST# is asserted after power-up in order to put the TAPcontroller in a known state. Failure to do so may cause improper processor operation.14.1.3 Instruction RegisterThe Instruction Register (IR) holds instruction codes. These codes are shifted in through the TestData Input (TDI) pin. The instruction codes are used to select the specific test operation to beperformed and the test data register to be accessed.The instruction register is a parallel-loadable, master/slave-configured 4-bit wide, serial-shiftregister with latched outputs. Data is shifted into and out of the IR serially through the TDI pinclocked by the rising edge of TCK when the TAP controller is in the Shift_IR state. The shifted-ininstruction becomes active upon latching from the master stage to the slave stage in the Update_IRstate. At that time the IR outputs along with the TAP finite state machine outputs are decoded toselect and control the test data register selected by that instruction. Upon latching, all actionscaused by any previous instructions terminates.The instruction determines the test to be performed, the test data register to be accessed, or both(Table 14-2). The IR is four bits wide. When the IR is selected in the Shift_IR state, the mostsignificant bit is connected to TDI, and the least significant bit is connected to TDO. The valuepresented on the TDI pin is shifted into the IR on each rising edge of TCK, as long as the TAPcontroller remains in the Shift_IR state. When the TAP controller changes to the Capture_IR state,fixed parallel data (0001 2 ) is captured. During Shift_IR, when a new instruction is shifted inthrough TDI, the value 0001 2 is always shifted out through TDO, least significant bit first. Thishelps identify instructions in a long chain of serial data from several devices.Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to theidcode instruction. When the TAP controller moves into the Test_Logic_Reset state other than byreset activation, the opcode changes as TDI is shifts, and becomes active on the falling edge ofTCK. See Figure 14-4 for an example of loading the instruction register.14-2 Developer’s Manual