Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller Unit2.7.2 FIQ1 Interrupt Status Register - FIQ1ISRThe FIQ1 Interrupt Status Register (FIQ1ISR) contains the current pending FIQ1# interrupts. Thesource of the FIQ1# interrupt can be the internal peripheral devices connected through the FIQ1Interrupt Latch. The interrupts which can be generated on the FIQ1# input are detailed inSection 2.4.3, Intel ® 80312 I/O Companion Chip: Internal Peripheral Interrupt Routing.The FIQ1ISR is used by application software to determine the source of an interrupt on the FIQ1#input and to clear that interrupt. All bits within this register are defined as read only. The bits withinthis register are cleared when the source of the interrupt (status register source shown in Table 2-3)are cleared. The FIQ1ISR reflects the current state of the input to the FIQ1 Interrupt Latch.Due to the asynchronous nature of the Intel ® 80312 I/O companion chip peripheral units, multipleinterrupts can be active when application software reads the FIQ1ISR register. Applicationsoftware must handle such conditions appropriately. In addition, application software maysubsequently read the FIQ1ISR register to determine when additional interrupts have occurredduring interrupt processing for the prior interrupts.Table 2-9 details the bit definition of the FIQ1ISR.Table 2-9. FIQ1 Interrupt Status Register- FIQ1ISR (Sheet 1 of 2)IOPAttributesPCIAttributes31 28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro ro rv ro ro roaaemdididiipipp2p1p0na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 Processor Local BusAddress0000 1708HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA= Not AccessibleBit Default Description31:06 0 Reserved05 0Application Accelerator Interrupt Pending - when set, an end of chain conditionhas been signaled by the Application Accelerator. When clear, no interruptcondition exists.04 0 2Performance Monitor Interrupt Pending - when set, at least one of theprogrammable event counters and/or the Global Time Stamp Counter contains anoverflow condition. Application software identifies the counter by reading theEvent Monitoring Interrupt Status register (EMISR).When clear, no interrupt condition exists.03 0 2 Reserved.2-12 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller UnitTable 2-9. FIQ1 Interrupt Status Register- FIQ1ISR (Sheet 2 of 2)IOPAttributesPCIAttributes31 28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro ro rv ro ro roaaemdididiipipp2p1p0na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 Processor Local BusAddress0000 1708HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA= Not AccessibleBit Default Description02 0 2 condition has been signaled by DMA channel 2. When clear, no interrupt conditionDMA Channel 2 Interrupt Pending - when set, an end of chain of channel activeexists.01 0 2 condition has been signaled by DMA channel 1. When clear, no interrupt conditionDMA Channel 1 Interrupt Pending - when set, an end of chain of channel activeexists.00 0 2 condition has been signaled by DMA channel 0. When clear, no interrupt conditionDMA Channel 0 Interrupt Pending - when set, an end of chain of channel activeexists.Developer’s Manual 2-13
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