Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.20 Prefetchable Memory Limit Register - PMLRThe Prefetchable Memory Limit Register defines the upper address (inclusive) of a prefetchablememory address range that is used to determine when to forward memory transactions from oneside of the bridge to the other. The Prefetchable Memory Limit Register must be programmed to avalue greater than or equal to the PMBR before the Memory Space Enable bit of the PrimaryCommand Register is set. When the value in the PMLR is not greater than or equal to the value ofthe PMBR once the Memory Space Enable bit is set, memory transactions on either side of thebridge will be indeterminate. The upper 12 bits correspond to AD[31:20] of 32-bit addresses. Forthe purposes of address decoding, the bridge assumes that AD[19:0], the lower 20 bits of thememory limit address, are FFFFFH. This forces a 1 Mbyte granularity on the memory addressrange.The VGA Enable bit in the BCR register forces the bridge to forward memory accesses in theaddress range from 0A0000H to 0BFFFFH from the Primary to Secondary and blocks addresses inthe same range from Secondary to Primary.Table 4-43.Prefetchable Memory Limit Register - PMLRIOPAttributes15 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rw rwrw rw rwrvrvrvrvPCI Configuration Offset26 - 27HIntel ® 80200 Processor Local Bus Address0000 1026HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:04 000HPrefetchable Memory Limit Address - This field is programmed with AD[31:20] of the top of the memoryaddress range to be passed down the hierarchy by the bridge.03:00 0H Reserved.Developer’s Manual 4-105